Multitraitement et processeurs configurables sur une plate-forme de haut niveau (French text)

The first part of this research looks at the possible uses of a configurable processor inside a network processor. A conception and partitioning methodology which is better adapted for configurable processors is proposed. This methodology advocates the usage of specialized instructions over coprocessors in order to quickly obtain a circuit with the desired level of performances.; The second part of this research looks at the usage of processors supporting multiple concurrent threads in hardware and therefore supporting rapid context stitches. It is a demonstrated fact that high communication latencies can have disastrous effects on the performances of a network processor. A hardware multithreaded processor seems to be able to hide the effect of such latencies. A model of a hardware multithreaded processor has been developed with the Xtensa simulator as a starting point. Afterwards, our simulations have shown that this modification can enable us to greatly accelerate the application and that this new acceleration is complementary to the one offered by customized instructions. (Abstract shortened by UMI.)...