Quasi-static energy recovery binary decision diagram logic (QSBDDL)

Due to the dynamic nature of their operation, most adiabatic logic families feature high switching activity. Furthermore, long latency caused by gate level pipelining of adiabatic circuits is unacceptable in a number of DSP applications. In this thesis, a new adiabatic logic style, named Quasi-Static Energy Recovery Binary Decision Diagram Logic (QSBDDL), is proposed. It remedies both of the above mentioned problems by combining quasi-static operation with complex logic gates and partial energy recovery and can be used in the implementation of arithmetic units in low power DSP systems.; To illustrate the design style, an 8 x 8 QSBDDL multiplier, featuring a novel partial product reduction architecture, was designed and implemented in a 0.18μm CMOS process. At a clock frequency of 100MHz, the implemented multiplier uses 50% and 20% less energy than equivalent multipliers implemented using conventional static CMOS circuits and quasi-static energy recovery logic (QSERL), respectively. Furthermore, the latency of the QSBDDL multiplier is reduced by a factor of 2.4 as compared to that of the QSERL multiplier.