| This work highlights bus-based architecture deficiencies by showing why they are not suitable for multiprocessor SoCs and then presents the network on chip concept. This type of architecture uses general notions associated with wide area networks. Those concepts are thus presented in this work.; In addition, it is possible to connect network components together in many ways, leading to various topologies. Several of those topologies are presented in this work and are discussed in order to highlight their pros and cons. Some NoC architectures are then presented to go along with the discussions.; A new NoC architecture, based on the token ring model and called RoC (Rotator on Chip) is the main focus of this thesis. Its architecture is easily scalable and can support a high utilization rate, which makes it less expensive in area than other networks while still preserving acceptable performance. Simulations show that RoC is slower than mesh-based networks on chip, while being less expensive. Having in mind the performance/cost tradeoff, RoC is very suitable when area and power consumption are significant issues. RoC also provides very good performance when used to process stream-based applications. (Abstract shortened by UMI.)... |
