| This thesis reexamines/revalidates an all digital built-in-self-test methodology meant for structural fault testing of PLLs. In this method, structural faults, to include drainsource short (DSS), gate-drain short (GDS), gate-source short (GSS), drain open (DO), source open (SO) and gate open (GO), are induced in specific subunits of the PLL such as the VCO, Charge-Pump and Loop-Filter. The response of the circuit, as a whole to any possible defect, is tested by detecting a change in impedance in the circuit under test. These changes can be detected by monitoring changes in the frequency of the VCO under constant current conditions. In the present work, the PLL circuit was synthesized using a hardware description language at a general level, and its operation was simulated in the RF (550--950MHz) and AF (10--50KHz) ranges, under fault-free and fault introduced conditions. |
