Development of a solid-state quantum computer: Single electron transistors and highly charged ion implantation

A proposal to manipulate phosphorous quantum bits in silicon has been studied as a new concept of the next generation computing. Quantum information systems in a silicon structure have a lot of advantages in terms of the scalability and the usage of advanced silicon technology. We studied solid-state quantum bit (qubit) schemes of dual phosphorous atom interactions in the crystalline silicon matrix. In this thesis, the developmental processes and the results from this study will be shown. This experimental approach includes a single ion implantation scheme into a registered position using highly charged ion sources and a single electron transistor read-out scheme using nanowires based on silicon fabrication technology.; Firstly, the single ion implantation scheme is based on slow (slower than the Bohr velocity: v < vBohr = 2.2 x 106 m/s) highly charged ions (SHCIs) extracted from the Electron Beam Ion Trap (EBIT) at the Lawrence Berkeley National Lab (LBNL). HCIs lose their electrons in an ion trap coupled with a high current density electron beam. An ion with few electrons can have a potential energy in a range of ∼10 to ∼100 keV The ion releases its potential energy in a time scale of ∼10 femto seconds (ultra-fast interaction) on a solid surface. This effect leads to electron emissions from the surface, which is proportional to the released potential energy. Hence, the efficiency of detecting single ions is higher than for singly-charged ions.; Secondly, we have formed 10--30 nm wires on a silicon wafer as a sensor to detect the phosphorous atom interactions inside the silicon solid matrix. Electron beam lithography (EBL) technology can pattern the wire size down to ∼10 nm scale. In this device, the sensitivity of a nanowire plays an important role in implementing the solid-state quantum computer.