Analysis and design considerations for AC coupled interconnection systems

As the process technologies for microelectronic integrated circuits continue to improve, both the amount of integrated, on-chip functionality and the number of required off chip interconnections (I/O) will continue to increase. These I/O will not only become more numerous but also will need to be packed densely and be capable of operating both with high bandwidth and low power. Packaging technology research is aimed at increasing I/O density and circuit research is underway to improve the bandwidth and power performance of I/Os. Advances are being made in each of these areas, but industrial roadmaps predict that these advances will not keep pace with the needed improvements. The research in this dissertation addresses this widening technological gap.;The central thesis in this work hinges on the recognition that arrays of densely packed, low-power, high-bandwidth I/Os can be created if the physical structure of each I/O is optimized for the type of information it must transmit. For example, the DC component of digital signals carries no information. Instead, digital signals contain information at frequencies well above DC (where the exact frequency spectrum of the information depends upon the edge rate of the data transitions). This can be exploited by recognizing that AC information can be transmitted across a boundary with non-contacting structures such as two plates of a capacitor or two coupled inductors. An I/O array can then be built with non-contacting structures for AC signals and direct contacts such as solder bumps only where DC signal transfers are needed. In this way, AC signal paths are freed from the mechanical constraints of direct, contacting structures and both the compliance and rework problems encountered in other high density interconnect technologies can be alleviated.;Capacitive and Inductive AC Coupled Interconnections are extensively analyzed and measured in this work and presented as a means to provide an array of sub-100mum pitched, low-power, multi-gigabit per second per pin interconnections. A packaging structure that enables AC Coupled Interconnections is also presented.