Design and FPGA implementation of complex multipliers using the logarithmic number system

In many real-time DSP applications, performance is a prime target. However, achieving high performance may be done at the expense of area and power dissipation. Attempts have been made to use alternative number systems to optimize the realization of arithmetic blocks, maintaining high performance without incurring prohibitive area and power increases. One such number system is the Logarithmic Number System in base two. Utilizing this system has the potential to result in highly optimized realizations of functions such as multiplication, division and square root.; Complex multiplication is one of the critical operations in various wireless applications. It normally requires a large area and consumes high power as the input width increases from 16 to 32 bits. Using the Logarithmic Number System can transform this operation into few additions and subtractions. The corresponding savings can even compensate for the additional costs of number system conversions at the input and output.; A digital complex mixer is a major component of a digital receiver, and a complex multiplier is one of its major building blocks. It performs frequency translation to isolate a given channel from a broadband signal. This thesis focuses on the design of complex multipliers based on the Logarithmic Number System. A major goal is to achieve low hardware implementation cost and small error rate while targeting an FPGA implementation.; The functional blocks of the complex multiplier include four logarithmic converters, four anti-logarithmic converters and six adders/subtractors. Error correction logic is embedded in the logarithmic and anti-logarithmic converters to minimize conversion errors. A 32-bit complex multiplier based on the proposed architecture has the best performance. It uses 67% fewer gates to implement and the delay x gate product is improved by 67% when compared to a design built with embedded LUT-based multipliers. All designs were verified at the RTL level and proper functionality was confirmed with Matlab to ensure the accuracy of the system.