| As across-chip interconnect delays can exceed a clock cycle, wire-pipelining becomes essential in high performance synchronous designs. Although wire-pipelining allows higher frequencies, it may change the circuit altogether because of the nonuniform increase in the latencies of the paths and cycles of the circuit. More importantly, it can reduce the delivered performance of a microarchitecture, since the extra flip-flops inserted may increase the operation latencies and stall cycles. Furthermore, the addition of latencies on some wires can have a large impact on the overall throughput while other wires are relatively insensitive to additional latencies. In addition, the high frequencies, coupled with high integration densities, have made operating temperature an important concern due to the nonlinearly increasing cooling costs.; Physical design, which determines the lengths of the multicycle wires and the spatial distribution of power dissipation sources, plays an important role in determining the throughput and thermal characteristics of a microarchitecture. Moreover, changes in the throughput can affect the power consumption levels through variations in the activity levels.; In this thesis, we examine two problems related to wire-pipelining and operating temperature, one each at the circuit and microarchitecture levels. First, we formulate a method to automatically correct the functionality of a wire-pipelined circuit. The proposed method finds the minimal value of the input issue rate slowdown required for a circuit as it affects the throughput of the circuit. The formulation may introduce extra registers into the circuit in the process of correction, and attempts to minimize the number of extra flip-flops thus added. The minimum area solution is cast as an instance of dual of minimum cost network flow problem and when experimented on circuits derived from the ISCAS benchmarks, the results suggest that wire-pipelining increases the overall throughput in most of the cases.; The second part of the thesis addresses interactions between microarchitecture and physical design stages. We propose a strategy for floorplanning that attempts to minimize the throughput loss that comes with wire-pipelining required to support higher clock frequencies. We use a statistical design of experiments strategy based on a multifactorial design, which intelligently uses a limited number of simulations to rank the importance of the wires, and this information is used by the floorplanner to optimize the throughput-critical wires by keeping them short. Our results over a number of SPEC benchmarks show improvements in the overall system performance for a number of frequencies when compared with an existing technique. Additionally, we compare a couple of simulation time reduction techniques that can be used to speedup the simulation strategy.; Next, we extend the throughput-aware floorplanning methodology to incorporate thermal issues. The approach uses instantaneous dynamic power dissipated in the blocks of a microarchitecture to find a placement that is optimal on a combination of the thermal and the throughput attributes. We also model the dependence between the throughput and power, and and uses transient analysis for thermal estimation. The thermal objectives that we consider are the peak and average temperatures. The results indicate significant improvements in both the peak and the average over a previously proposed approach. |
