Novel Approaches to Automated Digital Design Debugging in a Modern Development Cycl

The ever-increasing complexity of modern digital designs has introduced significant challenges to ensuring designs meet specification. Verification alone consumes up to 70% of the cost of designing a chip, with debugging comprising the majority of this cost. In recent years, advances in automated debugging techniques have alleviated this cost, but nevertheless are resource-intensive and offer only design-centric results. This thesis proposes two novel methodologies to address these problems. First, a dual-window approach to analyzing memory-locked errors is introduced. A sliding window is used to model inputs to memory while a fixed observation window is used to model memory outputs. Next, an extensible perceptron-based framework that ranks revisions based on their likelihood of having introduced an error is discussed. A perceptron is trained on past failures and their fixes, then used to make predictions on future failures. Experiments demonstrate the benefits offered by the proposed techniques.