| Three-dimensional (3-D) or vertical integration is a potent design paradigm to overcome the existing interconnect bottleneck in integrated systems. The major advantages of this emerging technology are the inherent reduction in wirelength and the ability to integrate heterogeneous circuits within a multi-plane system. To exploit these advantages, however, several challenges across different design abstraction levels, such as the architecture, physical, and technology levels, need to be overcome. In this dissertation, several issues affecting the design of 3-D circuits, primarily at the physical and architecture levels, are addressed.;Considering the importance of the interplane communication within a 3-D circuit, novel design methodologies and algorithms for the interplane interconnects are proposed in this dissertation. Algorithms for placing the interplane vias are proposed to lower the interconnect delay. Both two- and multi-terminal nets are considered. The proposed methodologies are the first to consider the heterogeneous nature of 3-D circuits; specifically, the impedance characteristics of the interplane vias.;Low latency interconnect, as compared to the long global wires, and the added design freedom due to the third dimension enable innovative topologies for on-chip networks. Several topologies for 3-D networks-on-chip that exhibit considerably enhanced performance as compared to 2-D topologies are proposed. Accurate analytic models that describe the interconnect delay and power within these networks have been developed.;The important global signaling issue of synchronization in 3-D circuits has been investigated for the first time. Several commonly used 2-D clock distribution architectures are combined into new 3-D synchronization network topologies. The design of these clock distribution networks and measurements from a 3-D test circuit are presented in the last part of this dissertation. Experimental results demonstrate successful operation at 1.4 GHz.;Summarizing, throughout this research thesis, many interconnect related problems in 3-D circuits have been addressed. Efficient and accurate solutions for these issues are proposed. These solutions are supported by results from an experimental 3-D test circuit. The proposed design methodologies described in this dissertation are intended to strengthen 3-D design capabilities, making this fascinating technology a promising solution for future integrated systems. |
