Design and evaluation of an 'FPGA based' hardware accelerator for elliptic curve cryptography point multiplication

Embedded systems are found in many applications in various fields such as defense, communications, industrial automation, and many more. Majority of these applications have security as the primary concern. Cryptography plays an important role in providing data security. Until recently, symmetric key encryption schemes were used for a majority of these applications. Now, however, asymmetric key encryption schemes such as Elliptic curve cryptography are gaining popularity as they require less computational power and memory and are still capable of providing equivalent security when compared to their counterparts such as. Elliptic curve cryptography was first introduced in 1985 and has always been around since. Scalar or point multiplication is the most time- and resource-consuming operation in elliptic curve cryptography. Improving the performance of point multiplication can improve the overall performance of elliptic curve cryptography.;The objective of this research was to design and evaluate a hardware accelerator for the elliptic curve point multiplication operation using Field Programmable Gate Array (FPGA) as the design technology. The performance evaluation was carried out by measuring parameters like maximum frequency of operation, resource utilization, and the speed up achieved by hybrid hardware/software implementation.;There are several algorithms that can be used for computing the product of scalar multiplication, for faster computation the binary non-adjacent form had been chosen for implementation in this thesis. The implementation was carried out using Verilog HDL. A system on programmable chip model (SOPC) was developed using the NIOS II soft processor. The associated firmware with the SOPC model was developed using the NIOS II IDE. The performance evaluation was carried out using the Timing Analyzer, Fitter, and Analysis and Synthesis modules in the Altera Quartus software. The hardware accelerator model has been successfully developed and implemented on the FPGA. The performance parameters for the hardware accelerated model have been evaluated and compared to the generic software implementation model and possible extension to this work has also been provided in this thesis. Performance evaluation of the entire system revealed that the designed system achieved a speed up of approximately 17 times compared to the software only implementation. Logic elements utilized by the Hybrid Implementation (Software -- Hardware combination) were found out to be only 6113 and the throughput per logic element was found out to be 1.484 Kbps thus making the designed system cost efficient, area efficient and faster compared to the software only implementation.