Study On The Process And Reliability Of 3D Packaging

In recent years,semiconductor packaging industry developing rapidly.As the functional diversification and complexity of the semiconductor product and the growing performance of the semiconductor devices,many novel applications,such as all kinds of MEMs sensors and portable electrical equipments.Due to the continually growing demands and requirments of the performance of the semiconductor products in the market,the density of the integrated circuit continuously increasing.However,the feature size of the lithography has gradually reached the limit,the development of moore’s law has encountered the bottleneck.Although the appeared 2.5D packaging based on inteposer technology and the 3D packaging based on lead interconnection had eased the contradiction,they are not the solution for the long term and more challenge could be brought in.Therefore,3D package based on TSV interconnection technology will finally become dominant solution,and extensive research has been implemented internationally.Although the govenment has put large amount of manpower and resources into this novel area,much problems still exsit and is waiting for study,and the developing of 3D packging industry based on TSV interconnection is relatively lag.In the thesis,a series of fundamental study has been implemented around the TSV interconnection,including TSV etching and plating,wafer thinning,Cu-Sn micro bump bonding and chip stacking.By research the difficult by simply,finally a 21 layer chip stacking module is fabricated by integrating the developed process and technology.The research results are as follows:By process experiments and FEA simulations,studied the influence law of the process parameters,such as wheel speed,wheel feed rate and wafer speed,for the wafer thining results,such as wafer warpage and surface quality.And find out the optimal process parameters based on the experimental data and the simulation results.Studied the material removel rate and the surface quality of the wafers in dry etching and wet etching.And with the help of temporary carrier technology,integrate dry etching and wet etching with the mechanical grinding and CMP process,thinned the TSV wafers to 40 um.Studied the integer bonding strength and thermal mechanical reliability of Cu-Sn micro bump bonding and Cu-Sn micro bump/BCB hybrid bonding.By contrast the difference,it is concluded that the Cu-Sn micro bump/BCB hybrid bonding modules has better integer bonding strength,yet better overall strength does’ t means better reliability of the microjoints.Due to the CTE gap between the BCB or other polymer adhesive and other materials,such as copper,tin and the silicon chip,the microjoints of Cu-Sn micro bump/BCB hybrid bonding module will more easily be destroyed in themal cycle tests.Based on FEA simulation results,a novel bonding structure is presented,by this bonding structure can improve the bonding strength of the microjoint and keep the equal thermal mechanical reliability.Combining nanoporpus copper fabrication technology,proposed nanoporous Cu-Sn bonding technology,and fabricated chips with nanoporous Cu-Sn micro bumps.By using optimized parameters of filp chip bondning process,fabricated chip stacking module.Then,compared the bonding strength of normal Cu-Sn micro bumps stacking module and nanoporous Cu-Sn micro bumps stacking module.It is found that the nanoporous Cu-Sn micro bumps can rapidly accelerate the alloy reaction and realize good bonding strength in a rather short time.Based on nanoporous Cu-Sn micro bumps bonding technology,a novel chip stacking method is developed.Comparing with traditional chip stacking method which stacking chips one by one from the bottom to the top,this chip stacking method can greatly increase the bonding time uniformity of every chip,and avoied the problem for the chips located at the bottom layer that endure too many bonding times,thus improved the maximum stacking layers of Cu-Sn micro bumps stacking,from 10-12 layers to about 21 layers.