Serial Code Accelerators for Heterogeneous Multi-core Processor with Three-Dimensional Stacked Memory

Asymmetric multi-core would be the pathway for future microprocessors with different cores performing different functionality. Of particular interest is the handling of serial and parallel code present in a given application. Performance improvement in multi-core microprocessors is limited by Amdahl's Law which states that speed up achieved by adding more cores gets saturated because of the presence of serial code in all applications. This calls for heterogeneous core integration of a fast core that accelerates serial code along with other CMOS cores that execute parallel component of the application. Performance improvement of parallel code can be improved by adding more cores, while higher clock rates can benefit serial. In either case, there is an associated memory wall problem due to limited bandwidth. We therefore require 3D stacked memory to overcome this problem. In this thesis, I evaluate high clock rate processors as well as shared memory processors with large number of cores with 3D stacked memory. Since clock rates for CMOS have tended to saturate due to wire scaling problems and excessive heat dissipation, one must look to an alternate three terminal device, which is compatible with CMOS i.e. BJTs. SiGe Hetero-junction Bipolar Transistor (HBT) BiCMOS process is used to build such fast digital chips that can clock in the 20-30GHz at reasonable power levels and densities. 3D memory stacked on top of a processor core can provide several advantages from wide bandwidth to multiport caches serving multiple cores. Memory Processor chip stacking reduces this Memory Wall problem by using a large number of vertical vias between tiers in the stack, for ultra wide bit path transfer of data and address information to and from various levels of cache. Chips have been successfully fabricated and tested in the 3D MITLL process as well as SiGe BiCMOS process. Thermal modeling for possible integration of these two processes has been carried out. The research is progressing towards the heterogeneous core integration with 3D memory.