High-performance subthreshold standard cell design and cell placement optimization

Digital subthreshold Complementary Metal-Oxide-Semiconductor (CMOS) circuits are gaining importance because of their ability to serve as an ideal low-power solution. Sub-threshold circuits can potentially replace superthreshold circuits in portable devices which execute non-performance-critical tasks, thereby increasing the battery life. The drawback of subthreshold circuits is their low operating speeds. By enhancing the speed of subthreshold circuits their application spectrum can be expanded.;Operating frequency is primarily dependent on the ON current (Ion) of the transistor. Increasing Ion would improve the frequency of subthreshold circuits. Ion is dependent on various parameters such as transistor threshold voltage (Vth), gate-source voltage ( Vgs) and supply voltage (Vdd). Ion can be increased either by boosting the V gs or by lowering the Vth of the MOS transistors through substrate biasing. This thesis presents a new approach to substrate biasing and compares the results with two existing biasing techniques. A new performance enhancement technique using charge boosting buffers to boost the Vgs of the transistors is presented. A performance-enhanced subthreshold standard cell library was built by implementing these techniques on a regular cell library for IBM 65 nm technology. The performance-enhanced cell library when implemented on the ISCAS benchmark circuits yielded a 10 times improvement in the frequency with approximately 2 times increase in the energy-delay product (EDP). The optimization problem for minimizing the overhead in the energy consumption without affecting the frequency is formulated as an integer linear program (ILP). The optimization algorithm yielded a 50% reduction in the EDP.