Advances in electronic packaging technologies by ultra-small microvias, super-fine interconnections and low loss polymer dielectrics

The fundamental motivation for this dissertation is to address the widening interconnect gap between integrated circuit (IC) demands and package substrates specifically for high frequency digital-RF systems applications. Moore's law for CMOS ICs predicts that transistor density on ICs will double approximately every 18 months. Packaging of ICs at the 32nm and 22nm nodes in the next few years will require 20mum (peripheral) and 80mum (area array) I/O pad pitch on the IC, which must be matched by flip-chip interconnection and substrate wiring pad pitch of the same 20-80mum dimension. System on a Package (SOP) technology pioneered by Georgia Tech PRC enables future "mega-function" electronic and bio-electronic systems through ultra-thin film component integration from the current 50/cm2 to over 10000/cm2. This puts added wiring density and performance demands on the substrate. The other driving force in this thesis research is the increasing adoption of high frequency wireless and wired communication pushing the need for package substrate materials that are stable into multiple GHz frequencies. The current state-of-the-art in IC package substrates is at 20mum lines/spaces and 50-60mum microvia diameter using epoxy dielectrics with loss tangent above 0.01. The research targets are to overcome the barriers of current technologies and demonstrate a set of advanced materials and process technologies capable of 5-10mum lines and spaces, and 10-30mum diameter microvias in a multilayer 3-D wiring substrate using 10-25mum thin film dielectrics with loss tangent in the <0.005. The research elements are organized as follows with a clear focus on understanding and characterization of fundamental materials structure-processing-property relationships and interfaces to achieve the next generation targets: (1) Low CTE Core Substrate. (2) Low Loss Dielectrics with 25mum and smaller microvias. (3) Sub-10mum Width Cu Conductors. (4) Integration of the various dielectric and conductor processes.