Device modeling and simulation of a static ram memory cell using carbon nanotube transistors

The VLSI technology has shrunk the size of the MOSFET transistors continuously over the decade. According to Moore's Law, the number of transistors per chip that yields the minimum cost per transistor has increased by a rate of roughly a factor of two per 18 months. These have significant effects on SRAM cell. They include random fluctuations of electrical characteristics and substantial leakage current. This disrupts the stability of the cell and makes them difficult to use in portable applications. One solution would be to use Carbon Nanotube Field Effect Transistors which prove to work better in the submicron dimension. They operate in the ballistic regime with high performance metrics. In this research, the 6T SRAM cell with MOSFET transistors is replaced by Carbon Nanotube Field Effect Transistors (CNFET). The performance of the device is evaluated.