The Investigation Of Ultra-Low Power HfO₂-Based Ferroelectric-Gated Carbon Nanotube Transistors

Hf O₂-based ferroelectric film has the characteristics of excellent ferroelectric performance,compatibility with existing integrated circuit manufacturing processes and strong scalability,the ferroelectric field effect transistor and ferroelectric negative capacitance transistor with the Hf O₂-based ferroelectric film as the gate medium have great application potential.They are considered as the strong candidates for the new non-volatile memory and low-power consumption transistors of the next generation.However,the Hf O₂-based ferroelectric thin film has the characteristics of polycrystalline and multiphase coexistence.The microstructures such as grain type,grain size,crystal orientation,and grain boundary are randomly distributed,which will cause the differences in electrical performance from device-to-device when transistor are scaling down.Therefore,it is difficult to achieve high-density integration.Besides,due to the unclear device physics,the performance and features of the fabricated ferroelectric negative capacitance transistors are rather different,which brings huge challenges to their logic circuit applications.Due to the limitations of silicon-based semiconductor technology,exploring the ferroelectric negative capacitance transistors which can realize power consumption,no hysteresis and high performance,especially to compete even surpass the silicon-based transistors also becomes the focus of research.Based on this,this thesis starts from the atomic layer deposition process of the zirconium-doped hafnium oxide(HZO)ferroelectric thin film,and explores the grain size engineering method for small-size ferroelectric transistor devices applications.The device physics of ideal ferroelectric negative capacitance transistors have been researched for the HZO-based ferroelectric negative capacitance transistors.Finally,we have developed carbon nanotube ferroelectric negative capacitance transistor with lower drain voltage,better drive current and transconductance than the silicon-based field-effect transistors(MOSFETs)with the similar gate length.The main innovative results are as follows:Firstly,based on the atomic layer deposition method,the effect of Hf O₂/Zr O₂precursor pulse cycle unit on the grain size and distribution of HZO ferroelectric thin films was studied with the same film thickness.It is found that 5/5 of the HZO has better ferroelectric properties,smaller average grain size and more uniform grain size distribution.Furthermore,the thickness of HZO ferroelectric thin film was reduced to about 2 nm to verify the effectiveness of the grain size engineering.(1)HZO thin films deposited with the precursor pulse cycle unit of 5/5 exhibits fined grain size and more uniform grain size distribution.This result shows that the optimization of the Hf O₂/Zr O₂ deposition cycle can improve the grain size and uniform distribution of the film.(2)HZO thin films deposited with the precursor pulse cycle unit of 5/5 exhibits better ferroelectricity with the remanent polarization 2P_r increasing to 41?C/cm²,which is about 2 times that of other deposition ratios of HZO films.(3)The thickness of the HZO film is further reduced to about 2 nm,and the 5/5HZO exhibits the smallest mean grain size of 9.3 nm and the smallest grain size distribution standard of 2.6.The single-point PFM measurement indicates that the ALD method improves the ferroelectric properties of the ultra-thin HZO film.possible regulation mechanism is as follows:the Zr O₂ layer with a suitable thickness can be used as a crystal nucleus control layer to make the final grain growth more uniform.The appropriate thickness of the Hf O₂ layer is used to suppress the size of the crystal nucleus and make the final crystal grain size smaller.Secondly,using the low-density carbon nanotube film and single-walled carbon nanotubes as channels respectively,we fabricated the negative capacitance transistors with different thickness of HZO gate dielectric and HZO/Al₂O₃ gate stack structures,respectively,to explore the gate capacitance matching,defects and ferroelectric domain characteristics influence on the performance of the transistors.The core design rules of ideal negative-capacitor components are obtained.More importantly,the feasibility of negative-capacitor transistors applied in logic circuits is verified.(1)It was found that for devices with negligible channel defect states,when the ferroelectric layer capacitance(||)is greater than the MOS capacitance(),the device appears non-hysteresis operation.When the||is closer to,the gate control amplification factor gets enhanced.When||is smaller than,the ferroelectric domain flips,which means that the ferroelectric hysteresis consistent with the memory characteristics appears.(2)The defect-rich carbon nanotube films and single-walled carbon nanotube negative capacitor devices were prepared and compared.The results show that although the defect capacitance can be used to increase theof the device,thereby increasing the negative capacitance matching factor in some degree.However,due to the charge capture and release process caused by the defect state is asymmetric during the forward and reverse sweeping process,the transistor exhibited obvious hysteresis and the poor stability.Suppressing defect in the channels is an important prerequisite for the design of stable negative capacitance transistors.(3)The single carbon nanotubes can achieve the unique quasi-one-dimensional channel region tending to ferroelectric single-domain regulation.It is found that the ferroelectric multi-domain characteristics will affect the on-state current and transconductance stability of the device.It is proposed that single-domain regulation is the optimal direction of the negative capacitance transistor.Finally,the remarkable advantages of carbon nanotubes in low power devices are analyzed.Then,the negative capacitance transistor is constructed with HZO as the ferroelectric layer and carbon nanotubes as the channel material.We experimentally verified that the negative capacitance transistor is stable without hysteresis and the subthreshold swing is below 60 m V/dec.In addition,at V_ds=-0.3 V,the normalized current and transconductance are better than that of silicon-based V_ds=-0.8 V,which proves the great application potential of combination of carbon nanotube with strong driving ability and HZO ferroelectric gate insulator in ultra-low power and high-performance integrated circuits.(1)The comparison of the gate control abilities of several main semiconductor materials including carbon nanotubes,silicon,molybdenum sulfide,and black phosphorus gated by ultra-thin dielectrics were derived theoretically.Combining the comparison of electrical parameters such as ballistic coefficient,mobility,quantum capacitance,effective carrier mass and so on,the significance of constructing negative capacitance transistors with carbon nanotubes combined with HZO ferroelectric materials are analyzed.(2)Experimentally,we verified that proper capacitance matching and device structure design in NCFET can simultaneously realize stability,no hysteresis,and a subthreshold swing below 60 m V/dec.Compared with the negative capacitance transistors based on other semiconductor materials,the negative capacitance transistors combined with carbon nanotubes and HZO exhibit better on-state current and transconductance.(3)The normalized on-state current and transconductance of negative capacitor transistors with gate length of 200 nm and 40 nm at V_ds=-0.3 V are much greater than those of 22 nm and 14 nm silicon-based Fin FET devices with V_ds=-0.8 V.