Design And Implementation Of Security Module Of Wireless Sensor Network

With the development of the Internet of Things,the application of micro-computing devices such as RFID chips and wireless sensor networks has become more and more widespread,bringing great convenience to people's lives.At the same time,how to ensure the security of information has attracted more and more attention.Because microcomputing devices generally have low computing power,limited storage space and energy supply,when designing information on these devices,it is often necessary to design a lightweight cryptographic algorithm with high efficiency and low resource consumption.Therefore,this paper proposes a technology to protect the information security of wireless sensor networks based on the lightweight PUFFIN algorithm: anti-coordination technology.Anti-coordination technology is to disturb the input data—called a variable code,change the value of the selected field,and then decode it when leaving the protection domain—recover the original value.The Anti-coordination technology for the data flow in the wireless sensor network can cut off the trigger information added by the attacker in the data stream and the trigger logic added by the attacker in the hardware,so that the hardware Trojan can't be triggered normally,that is,the function of actively resisting the hardware Trojan is realized.The anti-coordination module is composed of a pseudo-random number module,a key generation module,an update module,a transcoding module,and a decoding module.The pseudo-random number module generates a random number sequence for use as a master key and a random number.The key module generates a sub-key for data transcoding and decoding.The update module controls the logic of the entire system.The main function of the variable decoding module is to disturb and recover the data.This paper also gives the design criteria and related performance parameters of the decooperative module,and also completes the hardware implementation of the decooperative module on the Altera cyclone IV FPGA platform.The data stream is output The 11 CLK in the crypto module,while the pipeline is delayed by 8CLK.