Design And Implementation Of Dynamic Channelized Receiver

With the development of software radio technology,digital equipment is more and more close to the front-end antenna.Reasonable channelization technology can effectively improve the frequency measurement and phase measurement accuracy of acquisition signal.Due to the particularity of the working environment,the signals received by the digital receiver are often non cooperative signals,which often do not match the channel divided in the design,so the received signals may span multiple design channels.In this paper,a dynamic channelization separation system is designed and implemented when there are many different bandwidth signals in the receiving bandwidth.The operation of if data acquisition,Polyphase Orthogonal down conversion,signal synthesis decision,dynamic channelization separation are completed.The research contents of this paper are as follows:1.In the basic theory part of the receiver,from the basic principle of channelized receiver,the mathematical modeling and derivation of uniform channelization technology and instantaneous frequency detection algorithm are carried out,the conditions that the filter bank needs to meet when the signal is completely reconstructed are analyzed,and the non-uniform channelization method based on the modulation filter bank technology is selected as the implementation framework of this paper.2.In the part of data acquisition and preprocessing,the interface protocol of jesd204 b is combined with the actual requirements,and the problems that need to be paid attention to in the process of interface design are analyzed.The structure of digital down conversion realized by conventional polyphase filter method is improved,so that it can process high-speed data stream at FPGA working clock frequency.The steps of implementing jesd204 b interface on FPGA are described in detail,and the correctness of the implementation is verified by simulation on Modelsim.The polyphase digital down conversion algorithm is deduced and its implementation structure is given.The correctness of the algorithm is verified by MATLAB.3.In the part of dynamic channelization algorithm,the prototype filter of signal reconstruction filter bank is designed based on the principle of cosine modulation filter bank,and the simulation and verification diagram of the filter bank is given;the sub signal is sparse between each channel,and the noise of each sub channel comes from the same broadband signal at the same time,and a dynamic threshold adjustment using signal time-domain autocorrelation is given The method can dynamically adjust the decision threshold for multichannel signals and quickly detect the presence or absence of signals.On the basis of this method,combined with phase frequency measurement,the channel decision of the signal is realized.This paper presents a dynamic channel partition method which is easy to realize by combining the signal synthesis decision algorithm and the analysis synthesis filter structure.4.In the FPGA implementation part,the hardware platform of the digital receiver is designed,and the architecture of the whole system is briefly described.According to the actual demand index,the hardware structure of FPGA + FMC sub card + CPU is determined,the hardware principle block diagram is given,and the selection basis of FPGA and ADC chip is analyzed.This paper presents the top-level block diagram of the overall design and implementation in FPGA,as well as the implementation structure and implementation method of each sub module,including each module of the signal uniform channelization part,the signal comprehensive decision part,and the signal dynamic reconstruction part.Finally,the implementation steps of each module in FPGA are described,and the correctness of the implementation is verified by MATLAB and Modelsim.After the simulation and FPGA test,the implementation method can channelize the sub-band signal with different bandwidth in the broadband signal,and can effectively receive the cross-channel signal with different bandwidth.