| With the development of artificial intelligence,speech recognition,as a branch of natural language processing,has been widely used in mobile internet,smart home,automobile,medical,education and other fields.The constradiction between lower cost,lower power consumption and the huge computation load based on neural network has gradually emerged.In this paper,an accelerator based on configurable multiplier array and configurable memory architecture is proposed for speech recognition system.The accelerator system is simple to integrate.By configuring arrays,digital signal processing operations such as vector operation,matrix operation,FFT,etc.can be carried out with various data type as 8-bit,16-bit,32-bit real or complex data.Convolutional neural network CNN acceleration and deep neural network DNN acceleration can also be configured on this accelerator.The time division multiplexing is used to process the DSP function and neural network which reduces the complexity of system integration and can flexibly cope with different load ratios of digital signal processing and neural network in different scenarios.The micro-instruction system can change the internal structure of the accelerator to deal with a variety of algorithms and improve the applicability of the accelerator.When 256 8-bit symbolic multiplier arrays are used,the performance of the accelerator can be improved by 2.x-8.x times compared with the high performance DSP(HiFi-4)in API level and by 6.x times compared with the ARM Cortex-A7 NEON 4 core platform in system level.Convolutional and deep neural networks for speech awakening,speech synthesis and speech recognition can reach an average of198GOPS@500MHz.In the six microphone array voice interaction system,the integration of the accelerator and the low performance ARM Cortex-M4 MCU can fully meet the real-time requirements.When configuring 128KB local memory,the area after the layout is 1.53mm~2under TSMC 40nm technology.The measured average power consumption is 119mA@300MHz. |
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