Effect Of Surface Integrity On Following CMP Efficiency For Silicon Wafers Processed By Ultra-precision Grinding/lapping

Single-crystalline silicon wafer is the most widely used substrate material for manufacturing IC chips,and its processing quality directly determines the quality of IC chips.In the whole manufacturing process,there are damages on the surface and subsurface of the wafer after multi-wire-cutting.In industry,grinding and lapping are usually used to remove the surface damage layer.However,even if ultra-precision grinding and lapping are used to process silicon wafer,it is inevitable to introduce damage to the surface and subsurface of silicon wafer.The damage layer generated by grinding and lapping must be further removed by subsequent CMP process.The efficiency of subsequent CMP is greatly affected by the surface and subsurface quality.Therefore,the research on the surface integrity of grinding and lapping silicon wafers has guiding significance for the analysis of material removal mechanism and subsequent CMPefficiency.Through systematic experimental researches and theoretical analysis,the main conclusions of this paper are as follows:(1)The surface damage forms of ground silicon wafers is broken pits and grinding marks,while the ground silicon wafers with #3000B grinding wheel has only fine grinding marks;the surface damage forms of lapped silicon wafers are broken pits and scratches.(2)The surface roughness PV of silicon wafer ground with #120V,#600V,and #3000V wheel is 3.01 ?m,1.45 ?m,and 0.22 ?m larger than that of W0.4,W1.5 and W5 loose silicon carbide abrasives respectively,while the surface roughness PV of silicon wafer grinded with #3000B wheel is 44.85 nm smaller than that of lapped by W0.4 silicon carbide abrasive.(3)The forms of subsurface damage of ground silicon wafers are mainly median and radial cracks,and lapped silicon wafers are randomly extending cracks.The subsurface damage depth of wafers ground with #120V,#600V,and #3000V grinding wheels is 4.44 ?m,5.01 ?m,0.88 ?m larger than those of W0.4,W1.5,and W5 SiC.The subsurface damage depth of the wafer ground by #3000B grinding wheel is 0.41 ?m smaller than that of the W0.4 SiC lapped wafer,and the thickness of the amorphous layer and the dislocation layer of the wafer ground by #3000B wafer is smaller than that of lapped by W0.4 SiC,about 50 nm and 175 nm on average.(4)The hardness of the grinding and lapping silicon wafers with different particle sizes is lower than that of the polishing silicon wafer,but as the depth of subsurface damage decreases,the hardness of the silicon wafers surface also increase.The surface hardness of the #3000B lapping surface is closest to that of polished silicon wafer.The surface hardness of #3000B and #3000V grinding silicon wafers is 2.697 GPa and 2.043 GPa higher than that of W0.4 and W1.5 lapping silicon wafers,respectively.(5)In the CMP,the efficiency of the dam shape structure of the gorund wafers is better than that of the peak structure of the lapped wafers.Improving the grinding craft(eg,increasing the sparking time)can further improve the efficiency of the following CMP.