Research On Reliability-aware Runtime Performance Optimization Technology For 3D IC In Dark Silicon

As the characteristic size of integrated circuits becomes lower and lower,the number of integrated transistors on the chip becomes more and more,which will also bring high power density.In the end,because of the internal thermal constraints of the chip,many-core integration The system has recently entered the era of dark silicon.Dark silicon means that in a chip system,the processing cores cannot be turned on at the same time.Unfortunately,in 3D ICs,the problem of dark silicon because of the 3D IC stack structure brings higher power density,which worsens the problem of dark silicon in integrated circuits and severely limits the performance of the entire system.On the other hand,in 3D IC,the temperature distribution of the chip structure will have a very large impact on the reliability of the chip.Therefore,in 3D IC research,a real-time performance optimization technology that can consider reliability and dark silicon is urgently needed.Therefore,in the research work of this paper,we propose a technology that optimizes the real-time performance of a three-dimensional dark silicon chip that takes reliability into consideration.In order to ensure the real-time collaborative processing of the processor and cache structure,we introduce an novel greedy algorithm.The greedy algorithm in the new scheme roughly divides the optimization process into three steps:first,the cache structure configuration is fixed to determine the processor configuration;then the voltage/frequency ratio is adjusted according to the actual input;finally,the fixed processor configuration is used to determine the cache structure configuration.The final experiment also proved that this setup can effectively reduce the computational time complexity of the experiment.The new solution can use the processor or coprocessor to calculate many real-time configurations during the real-time operation of the 3D system:including the location of the processor core and cache structure,the number of active units in the cache structure,and the V/f levels of the processor core.These parameters can ensure the 3D IC to further optimize the performance of the system under the condition of temperature safety.Because the new method is used for optimization in the 3D system,and the processor and cache structure are collaboratively optimized,the parameters calculated by our new scheme,such as the processor's power budget,dynamically change with the state of the 3D system.The final comparative test also proves that such optimization results can bring better system performance to the entire system c ompared to the results of the existing metho.The optimization results of the new method make the temperature distribution of the 3D system more uniform,and can fully utilize the performance potential of the 3D structure.In the end,although the ral-time optimization of the new method brought some computational expenses,the.use of two types of 3D IC core number structures and a variety of test benchmark procedures throughout the experiment showed that the new method can be used to ensure the safety of 3D systems.The system brings higher system performance compared to the best existing method.The new method is superior to all existing research work in considering reliability and dark silicon.