Research On Decoding Algorithm Of LDPC Codes Based On Stochastic Computing

The LDPC codes are good codes that can approach the Shannon limit and can be decoded in parallel mode.The LDPC codes have been adopted in many standards,including IEEE 802.16(Wi MAX),IEEE 802.11(Wi Fi),and 5G.The main decoding algorithms of LDPC codes are belief propagation algorithm and belief propagation algorithm based on look-like ration.The complexity of these algorithms is too high to be used in the practical applications.In order to reduce the complexity of implementation,a simpler Min-Sum algorithm is proposed and is widely used in the practical applications.For high transmission wire and wireless networks,ultra high-throughput decoders are required.Decoders that use the Min-Sum decoding algorithm cannot be implemented in full parallel due to the complexity.Thus,the decoding speed cannot be further improved.To solve this problem,a method based on stochastic computing is applied to the decoder designs of the LDPC codes.The stochastic computing method use the random bit streams called Bernoulli sequences to represent the data value.In this way,the LDPC codes decoder based on stochastic computing deals with 1-bit streams,which can be implemented with the basic logical gates.Thus,the full parallel decoding can be achieved to obtain the ultra-high throughput.The LDPC codes decoding algorithms based on stochastic computing are almost all designed based on degree 6 variable nodes.Among them,the best performance of the decoder is MTFM algorithm.However,for the variable nodes with degree 3 and degree 4,the decoder can not have a good performance as expected and the convergence speed is not fast enough.On the other hand,the forward conversion module of the LDPC codes decoder based on stochastic computing consumes a lot of area.To solve the problems,several methods are proposed.(1)L2S method is proposed for the forward conversion module.The L2 S method consumes much less area compared with NDS before.Assuming that the code length of the LDPC code is N,the calculation part of the forward conversion module can be reduced from N to one,which reduces the resources.(2)A lot of comparators are used in variable nodes and forward conversion modules.According to the aricheritics of the stochastic computing,we propose a cascaded multiplexer(MUX)structure to achieve the function of gerenal comparator in this thesis.This paper proposes a method of using selector chains instead of comparators,which can save 43% of comparator resources.(3)This paper proposes the initialization of a re-random module based on bit flipping.The proposed method effectively speeds up the decoding convergence rate by 28%.(4)For variable nodes of degree 3 and degree 4,this paper proposes a method based on up-down counters and selectable side information.These two methods have the similar complexity as the MTFM-based method,and can accelerate the speed of 45% convergence and performance improvement greater than 0.15 d B.Finally,the paper gives suggestions for the structure design of variable nodes.