Digital Signal Conditioning And Design Of MEMS Pressure Sensor Chip

With the development of MEMS(Micro-Electro-Mechanical System)technology and Integrated Circuit Design technology,pressure sensors show the trend of digitalization,miniaturization,intellectualization and integration.The traditional pressure sensor has large volume and its output signal is analog signal,so it is easy to be disturbed.For temperature drift and non-linear calibration,the hardware calibration of peripheral discrete devices is also used,and the calibration accuracy is low.The digital pressure sensor of MEMS can be calibrated by on-chip microprocessor with high calibration accuracy.At the same time,it can be controlled by microprocessor to achieve performance optimization.Based on the integrated design of the existing ARM7 TDMI microprocessor in the laboratory,this paper completes the design of a low-power,18-bit output precision digital signal conditioning SoC(System on Chip)chip for the MEMS pressure sensor.The research work mainly revolves around the communication interaction between microprocessor and peripheral modules.The research focuses on digital downsampling filter,pressure calibration algorithm,memory organization structure and IIC serial port design of software and hardware cooperative control.The main work includes:(1)Understanding the development of the MEMS pressure sensor and the research status at home and abroad.The basic working principle of piezoresistive pressure sensor and the non-ideal factors affecting its performance are deeply studied.The popular calibration algorithms for temperature drift and non-linear compensation are introduced.Based on the existing experimental platform,an effective pressure calibration algorithm for solving temperature drift and non-linear compensation is determined.(2)According to the existing requirements,the system architecture of the chip is proposed.The chip integrates analog front-end circuit,microprocessor,digital down-sampling filter,calibration algorithm,memory,EEPROM(Electrical Erasable Programmable read only memory)control module,serial communication interface and other peripheral modules.(3)The analysis of the digital front-end and the design of RTL(Register Transfer Level)are carried out for the structure of the chip system.The model of digital down-sampling filter is instantiated by using the simulation model of MATLAB,and then the floating-point model is converted to the fixed-point model.In RTL implementation,CSD(Canonic Signed Digit)coding is used to reduce the area of multiplication operation,gated clock is used to reduce power consumption,and output is truncated.Pressure calibration algorithm uses state machine to realize time-sharing multiplexing of adder and multiplier,which reduces area and power consumption.For each peripheral logical address management,the MMU(Memory Management Unit)management unit is used to control.IIC serial communication module adopts the design method of hardware and software co-control,which makes the IIC serial port more flexible and can be applied to most IIC protocols on the market.Aiming at the existing IP EEPROM in the laboratory,the unique control logic of EEPROM based on APB bus control is designed.After completing the design,RTL simulation of the modules in the system is carried out,and the simulation results are analyzed.After the simulation meets the design requirements,the hardware and software co-verification of FPGA(Field-Programmable Gate Array)is carried out,and the verification platform of the system is built.The validation results are in line with expectations.Finally,some functional tests of the chip are carried out.The test results show that the EEPROM control module runs normally,and the hardware-software collaborative control of IIC can satisfy the inconsistent EEPROM of the two protocols.