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Design Of SPI And I/O Interface For Optical Transceiver Based On 0.13?m BiCMOS Technology

Posted on:2020-02-01Degree:MasterType:Thesis
Country:ChinaCandidate:C YangFull Text:PDF
GTID:2428330620956174Subject:Engineering
Abstract/Summary:PDF Full Text Request
In recent years,with the development of ultra-large-scale integrated circuits and advances in semiconductor technology,system on chip(SOC)is being used more and more widely,and there is an urgent need for accurate and fast information transfer between chips.A large number of peripheral interface standards have been generated,such as Serial Peripheral Interface(SPI),Inter-Integrated Circuit(I2C),Universal Serial Bus(USB)and so on.Among them,SPI is widely used for communication between processors and peripherals because of its reliable advantages.This paper introduces the design of optical transceiver SPI control module and I/O interface based on Global Foundries 0.13?m BiCMOS process.The external Microprogrammed Control Unit(MCU)can communicate with the SPI control module to achieve the purpose of configuring the optical transceiver registers,thereby implementing the control of modules in optical transceiver such as Clock Data Recovery(CDR),Transimpedance Amplifier(TIA),Equalizer(EQ)and so on.The SPI control module consists of sub-modules such as SPI interface module,register management module,frequency divider,reset module,and CRC encoding module,which implements the SPI protocol communication with the MCU and configures the optical transceiver register.The I/O interface contains input interface and output interface for providing functions such as receiving signals,output driving,and electrostatic protection for the SPI control module to ensure communication between the SPI control module and the MCU.The SPI control module designed in this paper supports up to 50 MHz SPI clock frequency,supports SPI four transmission modes,supports CRC check function,and supports APB protocol for data transmission between submodules.The I/O interface supports conversion between the signal level of 1.2V and 3.3V.At a signal rate of up to 50 MHz,the transmission delay is less than or equal to 1.1ns,the rise/fall time is less than or equal to 1.1ns,and the duty ratio is between 50% and 51.5%.The design analyzes the requirements,clarifies the design indicators,and completes the design according to the integrated circuit design process,through RTL design,circuit design,verification platform construction,presimulation,logic synthesis,back-end design and verification.Through simulation,the function and layout meet the design specifications and design requirements.
Keywords/Search Tags:SOC, SPI, APB, CRC, I/O Interface
PDF Full Text Request
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