A TSN Ethernet System Based On LZW Compression Algorithm

With the continuous development of network and communication technology,the development of the Industrial Internet is paid more and more attention.A time-sensitive CPS is one of the core technologies of Industry 4.0.A real-time communication network connecting sensors,actuators and controllers can ensure the precise realization of control cyber-physical systems.How to provide the Industrial Internet with an Ethernet solution that can increase the amount of information transmitted and performs a fixed delay time has become an important research topic.Based on the analysis of information compression and time-sensitive network research at home and abroad,a TSN Ethernet system based on the LZW compression algorithm is proposed.In this system,firstly,the LZW algorithm is used to perform hardware compression processing on the input Ethernet message.Secondly,Ethernet packets are scheduled and arbitrated to ensure the transmission delay time a certain value.Thirdly,logical function verification and actual testing are implemented in the TSN system.The main research includes:(1)Based on the analysis of the LZW compression algorithm,a hardware compression circuit of the LZW compression algorithm is designed with FPGA,including a cache control module,streamlined state machine control module,and dictionary storage module.Data transmission can be accelerated with an asynchronous FIFOs,while the utilization of internal resources of FPGA can be improved with a streamlined state machine module.The hardware design module of LZW compression algorithm is written in Verilog HDL language.(2)The module functions of TSN Ethernet such as frame format,clock synchronization,bridge network,gate control scheduling and frame preemption are analyzed.Using a fast and scalable pipeline priority queue architecture designed by the University of California,the message output management system is implemented,Improve the scheduling algorithm of TSN Ethernet,divide the hardware system into input module,flow table and output module,and adopt time-sensitive network scheduling algorithm and arbitration mechanism to ensure a fixed delay time,realizing the real-time characteristics and fixed delay of TSN Ethernet time.(3)Under the case of the path test and TSN special test,the packet loss,current interruption,out-of-sequence and CRC check are tested in the Vivado Simulator simulation software,and this method is verified the correctness of the functional logic of the design.The compression rate is also measured on the AX7325 development board.The network debugging assistant and Wireshark are performed to physical measurements to meet the delay time design index.Through the experimental data,it can be known that the FPGA-based LZW compression scheme proposed in this thesis can achieve real-time lossless compression.Compared with software compression,the average compression speed of hardware compression is increased by about 9.08 times,and the energy efficiency ratio by about 65.5 times.In the Industrial Internet,the TSN Ethernet system with the LZW compression algorithm can be used to obtain a certain delay time and improve the transmission speed of effective information.