Research And FPGA Implementation For Partial Disguised Face Recognition Based On Deep Neural Network

In recent years,face recognition in the field of video surveillance has received widespread attention.Tracking criminals through video surveillance has greatly improved the detection rate of cases.But criminals may evade the surveillance system by disguising.As an important branch of face recognition,disguised face recognition is of great significance in combating criminals and maintaining public order.At present,there are few researchs on disguised face recognition.The recognition accuracy of the existing algorithms is not high and the robustness is not strong.Aiming at these problems,this thesis proposes a disguised face recognition algorithm based on deep neural networks.By improving the network model,the accuracy of the recognition algorithm is improved.The FPGA design of the recognition algorithm is implemented on the FPGA to achieve the acceleration effect of the algorithm.The main research contents are as follows:A disguised face recognition algorithm based on deep neural network is proposed.By improving the Squeeze Net network model and combining it with the Face Net network architecture to extract features,the triplet pairs are used to implement the model training.Finally,the feature differences between different images are compared for the recognition process.The feasibility of the method is analyzed through experiments under different parameters.Experimental results show that the recognition accuracy of the algorithm proposed in this thesis is close to 90%.Compared with other algorithms,the recognition accuracy has a certain degree of improvement.The FPGA design of the face recognition algorithm is completed.First,the operation process of the recognition algorithm is analyzed.The parallelism,operation process and operation amount in the neural network inference process are analyzed.Secondly,the task is divided into hardware and software.The overall design scheme of the recognition algorithm is completed.Finally,corresponding operation units are designed for various operations in the neural network.And each operation layer is designed according to these operation units.The face recognition algorithm is implemented on FPGA.Based on the FPGA design of the recognition algorithm,the software and hardware implementation process of the recognition algorithm is formulated.The IP core of each layer of the network model is designed for hardware acceleration.The ARM processor is used to realize the system flow control and related software operations.The experimental results show that the operation speed of the hardware is 2.69 times higher than that of the CPU.This approach has a better acceleration effect.