Research On Hardware Acceleration For RBRIEF Descriptor And RANSAC Algorithm

Image feature point extraction is an important research topic of computer vision.Nevertheless,the computational complexity of most image feature point extraction algorithms is high.In practical applications,the traditional PC platform is difficult to meet the needs of real-time feature point extraction.Therefore,using FPGA(Field Programmable Gate Array)platform to accelerate the algorithms has been becoming a research hotspot.Meanwhile,the matching results obtained by feature point extraction algorithm usually contain an overwhelming number of mismatches,which can be effectively eliminated by RANSAC(Random Sample Consensus)algorithm.Aiming at the needs of real-time and robustness of image feature point extraction algorithms,this thesis designs hardware acceleration schemes based on FPGA of the rBRIEF(Rotated Binary Robust Independent Elementary Features)descriptor construction algorithm and RANSAC algorithm.In the hardware implementation of rBRIEF algorithm,the method of quadrant segmentation and angle search is used for generating the orientation of feature points,and the extraction template of rotating sampling points is used for generating descriptors.Then,this thesis designs a parallel circuit structure of the orientation generation module and descriptor generation module,and implements the generation of rBRIEF descriptors in a single cycle,which greatly speeds up the frame rate of image processing.RANSAC algorithm hardware accelerator proposed in this thesis is applied to filter matching results of feature points.According to the application scenario,this thesis uses the combination of affine transformation model and Chebyshev distance to determine the correct relationship between matching points.In terms of circuit design,a data shunt buffer circuit and a pseudo-random address generator are designed for pseudo-randomly sampling the original match pairs.Aiming at the iterative characteristics of RANSAC algorithm,this thesis proposes a novel model evaluation circuit with a single-line systolic array structure,which realizes the parallelizing processing of the iteration of RANSAC algorithm.The proposed rBRIEF descriptor construction module and the RANSAC hardware accelerator are combined with SURF(Speeded-Up Robust Features)feature point detection circuit implemented by the research group to construct an image feature point extraction and screening of matchings system on the Zynq-7000 platform.At the frequency of 100 MHz,the system achieves a processing speed of 325 fps for image with 640×480 resolution.The experimental results show that the design of this thesis is robust to image blur,illumination and rotation changes under the test of standard dataset and real pictures.In certain actual scenes with a large rotation of 150°,the coincidence rate between its matching result and the software Open CV result can still reach more than 85%.In the case of setting 800 iterations to screen 384 matching pairs,the RANSAC algorithm hardware accelerator designed in this thesis only takes 0.2 ms.