Study On Performance Optimization Of Metal Oxide TFTs Digital Circuit Based On Differential Logic

Metal oxide thin film transistor(MO TFT)has a wide application prospect because of its high carrier mobility,good transparency and simple fabrication process.The integrated circuits based on MO TFT are developing towards higher integration,larger scale and more complex,which also puts forward more new requirements for circuit performance.However,due to the limitation of active layer materials and process conditions,high-performance P-type MO TFT could not be fabricated to realize complementary circuits,which inevitably affects the power consumption,speed and stability of the fabricated circuit.It is difficult to meet the high-performance requirements.Therefore,it is very important to study the performance optimization of unipolar MO TFT circuits,which consist of transistors of just N-type only.In this thesis,a differential logic unit is designed to solve the static power consumption issue of traditional logic units in unipolar n-type circuits.The proposed differential logic unit uses the cross coupled positive feedback structure to eliminate the static current path,which can effectively reduce the static power consumption.The simulation results show that the differential logic unit can provide complementary output signals,which is also beneficial to reduce the logic complexity.At the same time,good output driving ability is achieved and the static power consumption is close to 0.In this thesis,we use the proposed differential logic unit to improve the bottom module of the circuit,and realize the reduction of power consumption and delay for radio frequency identification(RFID)tag circuit and carry ahead adder circuit,respectively.Aiming at the power consumption issue of RFID tag circuit,differential logic is used to improve the decoder circuit inside the tag.According to the test results of the chip,the power consumption of the whole circuit is reduced by more than 20% and the output data rate can be kept at a high level.The optimization scheme is suitable for the application scenarios with high power supply voltage.Furthermore,based on the pull-up control principle,the built-in clock generation circuit of the tag is improved.In combination with the differential logic decoder,the power consumption of the whole circuit is reduced by at least 40%.This optimization scheme can meet the application scenarios with more stringent power requirements.The two optimization schemes do not need to add extra transistors,and the optimization effect is not sensitive to the change of power supply voltage.Aiming at the issue of carry propagation delay of the carry look-ahead adder circuit,the circuit topology is redesigned using differential logic combined with complementary transfer transistor logic.This proposed topology reduces the stacking of gate circuits and the number of transistors.The simulation results show that the transmission delay of the 4-bit carry look-ahead adder is reduced by more than 20%,the power consumption of the carry-link is reduced by 73%,and the output swing and driving ability of the 4-bit carry look-ahead adder are the same as that of the traditional structure.In order to get a more universal performance improvement scheme,this thesis mainly focuses on the improvement of the logic structure of the circuit,which brings a new perspective for the performance optimization of MO TFTs integrated circuits.