Multi-mode Dynamic Switchable Low-power Processor Design

As the core component of the computer,the processor is widely used in the Internet of Things,portable devices,artificial intelligence and other fields.Because it is not appropriate to replace the power supply in the terminal nodes of the Internet of Things,the requirements for low power consumption are high.With the development of the Internet of Things,the data processing and transmission stage contains a large number of complex operations.At this stage,the processor needs to have high enough performance.Therefore,low-power data collection and high-performance data processing and transmission are the key to ensure the normal operation of IoT applications.This paper proposes a multi-mode dynamic switchable low-power processor design scheme based on the RV32IM instruction set for different application scenarios in IoT applications.First of all,in order to analyze the power consumption characteristics of the processor,it is necessary to test the power consumption of different units constituting the processor.This paper designs the RISC-V five-stage pipeline processor architecture and tests its power consumption.The power consumption of the pipeline register,general-purpose register,multiplication unit,and division unit is high,which is 83.7%of the total power consumption;Secondly,in view of the phenomenon that the power consumption of some modules in the processor is relatively large,the concept of mode switching is proposed,and the power switch of the module is dynamically controlled in different working modes to reduce power consumption.Using System Verilog language to realize the hardware circuit structure design of multi-mode dynamic switchable low-power processor;Finally,power gating technology is used for low-power design,and UPF is used to describe the power connection during the process.The working mode switching of the processor adopts the way of software and hardware cooperation.Finally,a processor including high-performance mode,low-speed mode,low-power mode,and ultra-low-power mode is realized.In this paper,the DMIPS program is used as a test benchmark.At an operating frequency of 1MHz,the TSMC 40nm process is used to perform low-power functional simulation,logic synthesis and power analysis on a multi-mode dynamically switchable low-power processor.The results show that,compared with the five-stage pipeline processor,the hardware resources of the multi-mode dynamic switchable low-power processor have increased by 7.12%,and in high-performance mode,the power consumption of the processor has increased by only 9.0%.In low-speed mode,low-power mode,and ultra-low-power mode,the power consumption of the processor has been reduced by 32.3%,70.2%,and 77.9%,respectively.Multi-mode dynamically switchable low-power processors have achieved significant power optimization with less hardware overhead.