The Design Of Frequency Doubler And LNA Based On CMOS Technology

Due to the depletion of low-frequency communication band resources and the demand for highspeed broadband wireless communication,the frequency band used by wireless communication is bound to develop to the high frequency band.Compared with other compound processes,CMOS process has the advantages of low cost and high integration.In addition,The Low-noise amplifier and frequency multiplier are two important components in the RF front-end circuit.The low noise amplifier is generally used as the preamplifier of the receiver,which determines the noise characteristics of the whole receiving system.The frequency multiplier is often used in transmitters to generate high frequency signal.Therefore,it is important to study how to design a frequency multiplier and a low-noise amplifier operating at high frequency using a CMOS process for the application and development of modern communication systems.First of all,the CMOS process and the MOSFET used in the circuit design of this thesis is introduced,and the transmission line theory in RF circuit design is summarized.In addition,the passive components such as inductance and capacitance,which are commonly used in RF integrated circuits,are introduced,and their implementation structure and parasitic parameter model are described.This thesis also introduces balun,which is commonly used in the balanced or differential structures,and analyzes the difference of balun with different structures.Subsequently,a D-band broadband frequency doubler based on 65-nm CMOS technology is proposed in this thesis.This circuit uses a single-balanced topology to achieve the generation of the second harmonic signal and the suppression of the fundamental wave.At the same time,the spiral Marchand balun with a compensation line is used to achieve single-ended to balanced structure conversion and expand the circuit bandwidth.The output frequency of this frequency doubler is110～170GHz,the DC power consumption is 2.3m W,when the input power is 10 d Bm,the conversion gain is-13 d B to-10 d B,the fundamental wave suppression is greater than 19 d B,and the relative bandwidth is 50%.The chip size is only 0.45×0.58mm2.Finally,based on the 180-nm CMOS process,a 28 GHz low-noise amplifier is designed.The low-noise amplifier adopts a three-stage common source structure,in which the amplifiers at all stages share the same voltage source and the inter-stage matching adopts a distributed method to improve the overall bandwidth.From the simulation results,the gain of the low-noise amplifier is greater than 11 d B in 23～30 GHz.At 28 GHz,the gain is about 16 d B,the noise figure is 4.9 d B.the DC power consumption is 28.8m W,and the total area of the chip is 1.2×0.69mm2.Based on the CMOS technology and the simulation software ADS and Cadence,the design of aD-band broadband frequency doubler and a 28 GHz low-noise amplifier is completed by combining theory with simulation in this thesis.It has a certain reference significance for the design of CMOS RF integrated circuits with high frequency band.