Research On 3D Flash Error Control Technology Based On LDPC Code

The digital storage industry is a high-tech industry.As a representative of high-density storage technology,Flash technology has become the mainstream of applications in various fields with absolute advantages.Breakthrough of Flash technology Traditional flat-panel Flash has evolved into a 3D Flash stage with greater storage capacity.3D Flash is based on the traditional Flash memory structure,and the stacking method of the storage unit is extended to the vertical direction,which greatly improves the storage capacity of the Flash when the physical size of the storage unit is difficult to break.However,the capacity increase is at the cost of double the Flash bit error rate.Therefore,3D Flash puts forward higher requirements for the error correction capability of the Flash controller.The traditional error correction code can no longer meet the demand for such high error correction performance.Low Density Parity Check(LDPC)codes with more powerful theoretical error correction capabilities play an important role in the field of 3D Flash error correction.Since the overall bit error rate of Nand Flash increases with the use time,it is necessary to adjust the transmission rate of the information.The traditional TLC Flash processing information transmission rate change requires multiple pairs of codecs and decoders,and the hardware implementation complexity is high.The TLC Flash logical bit error rate is not considered.For the above problem,a rate-compatible original LDPC code suitable for TLC Flash channel is proposed by using the codeword extension method.The original LDPC code is optimized.The distribution of the variable node degrees makes it suitable for the bit error rate case where the TLC Flash logic bit is unbalanced.The simulation is also carried out under the 3D TLC Flash channel.The simulation results show that the proposed rate-compatible LDPC code has a signal-to-noise ratio performance of 0.26 d B higher than that of the PEG-based irregular LDPC code.Secondly,with the improvement of the overall bit error rate of 3D Flash,the reliable storage time of the data is shortened,and the lifespan will be shortened.Therefore,how to improve the service life of 3D Flash is an inevitable problem.Since 3D TLC Flash has a small proportion of data error bits in the actual storage process,the traditional 3D TLC Flash controller directly checks and corrects the read data through the LDPC error controller,and the calculation amount is large and delayed.The problem of high and easy decoding iterations affects the error correction performance.Secondly,after multiple erasing of Flash,as the data storage time increases,the LSB logical page error rate in some storage areas will increase significantly.When the bit error rate exceeds the error correction capability of the LDPC error controller,even if other logical pages in the memory area can be correctly corrected,the memory area is still judged as a bad area and affects the reliability of the flash.Aiming at the above problems,this paper proposes a 3D Flash error control method based on cyclic redundancy check and bit interleaving LDPC code.This method uses CRC to judge whether the data is erroneous or not,and then performs LDPC error correction after the error.The high degree reduces unnecessary waste of error correction performance,and secondly,the bit interleaver is used to change the order of storing bit information in the 3D TLC Flash logical page,thereby reducing the unnecessary bad area caused by the excessive error rate of the LSB single logical page.Improve 3D TLC Flash data storage reliability.The simulation results show that compared with the traditional 3D TLC Flash error control method,the error control method proposed in this paper reduces the bit error rate of 35.7% of the LSB single logical page and prolongs the reliable storage time of 3D TLC Flash data.