Design Of LTE Downlink Synchronization For LEO Satellite Communication On FPGA

With the rapid development of broadband mobile network,it is very imperative to implement a global broadband communication system.Long term evolution(LTE)can provide high quality communication services.But due to the deployment difficulties,it is not yet available to some users living in remote areas.Low earth orbit satellite communication service can cover all parts of the world,therefore the research on the fusion of low earth orbit satellite communication and LTE has been a hotspot.However,the application of LTE technology to low earth orbit satellite communication will also face many difficulties.The characteristics of satellite channel,such as large time delay,large frequency offset and low signal-to-noise ratio have a great impact on the correct reception of signals.In LTE system,the timing and frequency offset estimation of signal sent by the base station are estimated and compensated in the process of downlink synchronization.Therefore,this paper mainly studies the LTE downlink synchronization scheme in low earth orbit satellite communication environment,and implements the scheme on field-programmable gate array(FPGA).Firstly,the research status and significance of low earth orbit satellite communication,LTE,downlink synchronization algorithm and implementation is described in the paper,and some related technologies of LTE system are introduced.Secondly,simulation,comparison and analysis of timing estimation,integer and fraction carrier frequency offset estimation,cyclic prefix(CP)type detection and secondary synchronization signal(SSS)detection algorithm is down under the typical low earth orbit satellite channel model.And a scheme of LTE downlink synchronization with good performance under the condition of satellite channel is given.For timing estimation,AHC(almost half complexity)algorithm with excellent performance and low algorithm complexity is selected.The algorithm makes timing estimation based on primary synchronization signal(PSS),the estimated period is 5ms,which can keep up with the change of satellite communication delay.At the same time,to avoid the influence of integer frequency offset on timing position,the combination of timing and integer frequency offset estimation is used,which enhances the performance of algorithm.According to simulation results,the algorithm can estimate the integer frequency offset of 30 KHz in satellite communication.For CP detect and fractional frequency offset estimation,M points sliding self-correlation algorithm is selected,and the general coherent detection algorithm is used to detect SSS.According to simulation results,the two algorithm have good performance under the condition of low signal-to-noise ratio,which can meet the need of satellite communication.Then the scheme of FPGA design is divided into data and timing control,cache,sliding control,PSS detect,CP detect,frequency offset compensation,timing adjustment,orthogonal frequency division multiplexing(OFDM)demodulation and SSS detect modules,the modules are respectively studied and implemented in the paper.In the implementation scheme,multiplication is converted to xor to simplify computing during SSS descrambling process.The time reuse of similar processes in PSS detection and CP detection avoids the waste of hardware resources.Later,a verification platform is built to verify the function and performance of FPGA module.According to the integrated results on Xilinx XZCU2 EGS chip,the major hardware resource consumption of the implementation scheme is within 20%,the maximum working clock of the circuit is 183.15 MHz.The results show that the scheme has correct function and satisfactory performance.