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The Hardware Implementation Technology Of Intrapulse Time-frequency Feature Extraction And Modulation Recognition

Posted on:2020-06-07Degree:MasterType:Thesis
Country:ChinaCandidate:J T XuFull Text:PDF
GTID:2428330602451421Subject:Engineering
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The pulse signal reconnaissance system,whitch intercepts the radar signals,digitize the signals and extract the feature parameters,and then perform sorting identification and intrapulse analysis to obtain the location and essential information of the radiation source,plays an important role in electronic support.However,the complex electromagnetic environment and the ever-changing battlefield situation nowadays not only require the reconnaissance system to accurately identify the pulse signal under low SNR,but also obtain useful information from it,and must also be able to perform hardware processing in full real-time,thus improving interception.Probability,even requires the reconnaissance system to be miniaturized and portable,to meet the needs of individual combat operations.In recent years,with the development of image processing technology,intra-pulse type recognition technology based on time-frequency analysis and image recognition has been proposed in many literatures.This method is better than other algorithms in terms of noise resistance and robustness.The identification has strong versatility,making the identification system easy to upgrade.At present,this method is a hot research direction in the field of signal reconnaissance.However,most of the literature research at this stage only stays at the stage of software simulation,and does not combine hardware to implement this method.Therefore,this thesis studies the design method of pulse reconnaissance receiving system based on time-frequency image processing method from the perspective of FPGA heterogeneous parallel system.The main theories and techniques involve digital downsampling,time-frequency image generation and deep convolutional neural network sorting.And give their parallel implementation and the corresponding performance analysis.In the research process,this thesis uses parallelization and pipeline technology to achieve broadband down conversion,time-frequency transform and efficient processing of convolutional neural networks.This thesis combines the current research results of pulse time-frequency feature extraction and heterogeneous parallel computing,and carries out the following research work: 1.Introduce the modulation types and features of typical three pulse signals,and the basic principles of the pulse signal reconnaissance system.The advantages of frequency domain channelization for wideband received signals are analyzed.The principle and features of STFT transform and WVD are analyzed in depth,and the engineering algorithm is proposed.In order to effectively identify the modulation features from time-frequency images,this thesis introduces a deep convolutional neural network,which describes deep convolutional neural networks,BP neural networks and traditional machine learning from three aspects: sparse connection,parameter sharing and pooling downsampling,compared to the advantages.2.From the perspective of hardware design,the process of generating time-frequency image of pulse signal is analyzed.Combining the specific engineering parameters,a multi-level orthogonal down-conversion hardware solution is proposed for wideband received signals,and the 3200 MHz single-channel wideband signal is converted into 25 MHz narrowband quadrature signal,which reduces the hardware difficulty of intra-time time-frequency feature extraction and recognition.Aiming at the hardware implementation of short-time Fourier transform,the implementation scheme of multi-phase decomposition and pipeline combination is proposed.The principle,process and characteristics are analyzed in detail,and the final hardware performance is given.In order to realize the gray-scale of timefrequency matrix,this thesis designs an efficient gray-scale mapping circuit.3.From the perspective of hardware design,a deep convolutional neural network classifier with two layers of convolution is analyzed and implemented.According to the heterogeneous parallelism of the hardware platform,a neural network with two layers of convolutional layer is designed.Detailed feasibility analysis solutions and hardware solutions are given.The parallelization of the calculation process of the convolutional layer,the pooling layer,and the fully connected layer,and the detailed complexity analysis,fully exploited the advantages of the heterogeneous parallel system.4.The pulse signal reconnaissance processing system is built by using Xilinx heterogeneous parallel system ZYNQ-7000.The process of using AXI4 bus as module interconnection protocol and address mapping is introduced in hardware.The system startup,system driver,User Interface and application program are described in software.This article uses MATLAB and the software radio system to generate a large sample set for testing and verification.The verification structure is analyzed in terms of correctness,real-time and resource usage.The verification results show that the system designed in this thesis has a good advantage in terms of correctness,real-time and resource usage.At the same time,the platform implemented in this thesis has the advantages of miniaturization and low power consumption,and has important reference significance in engineering practice.
Keywords/Search Tags:Radar Reconnaissance, Feature Extraction, Time-Frequency Analysis, Convolutional Neural Network, Heterogeneous Parallel
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