Software Performance And Status Analysis Using HPM

Performance analysis for high performance computing plays an important role in domains of science researches and large scale application system. Performance improvement of software can save large amount of money on the one hand through avoiding unnesseccery hardware investment and upgrade; on the other hand, performance improvement can help us exploring the hidden characteristics of the computer system, so we can reach the performance limitation as possible as we can.The company such as telecommunication carriers always hope to provide better quality of service(QoS) under current system including software and hardware. Carriers also want to monitor the applications online all of dayes to find bugs in software or defects in hardware in time. Two of the requiements need some sophisticated estimations about the system on performance and status with low cost. Traditional methods such as emulation can do little about it, it has to introduce some new arts. On the path of modern computer and CPU designing, the registers, level 1 cache, level 2 cache on the chip and level 3 cache on the mainboard, plus RAM, hard disk or floppy disk or flash disk, make up of the modern multi-hiberarchy storage architecture. According the distance away from CPU core near to far, the acces speed of memory falls down from faster to lower, but the cost from higher to less. Excepting algorithms self, the software performance analysis and optimization always relate to the multi-hiberarchy storage archtechture, trying to utilize the nearside storage media such as register or level 1 cache and reduce actions on farside storage, and try to reach a linear performance, i.e. the computing performance only relate to the speed of CPU clock.For the goal of improving performance and monitoring the status of CPU dynamic behavior, manufactures of CPU such as Intel, HP, Sun, IBM added some especial registers to record performance data such Level 1 Cache Missses, Branches Mispredicts, Translate Lookaside Buffer Misses. These registers are embedded in the CPU chip, and sampled parallel with the normal instructions pipeline. These registers are called hardware performance monitoring counters or HPM events.Because HPM events can record performance data such as Level 1 Cache which revealing software performance, from year of 2000 to now,many performance analysis models and tools using HPM events be introduced. SciDAC center setup an successful anlysis model named PERC. The goal of SciDAC center is to develop a science for...