Design And Implementation Of Hardware Packet Classifier Coprocessor

Packet classification is the basis of many core network technologies.Its classification speed will directly affect the development of the next generation network.At present,the main hardware method to realize message classification in the industry is to use TCAM.TCAM has three-state characteristics.It has great advantages in storing fixed values and prefix values of classification rules,but it can't directly store range values.Even if it is converted into fixed values or prefix values for storage,it will occupy too many TCAM entries,resulting in range expansion,which reduces the space utilization of TCAM and greatly increases power consumption.In this context,we use SRGE to process the range fields in the classification rules.The coded rule entries are stored in the TCAM table according to the second-level C-TCAM structure.When the two schemes are combined,the range expansion factor is only W-2 in the worst case,where W is the width of the range fields.This scheme only stays at the control level,and the purpose of this paper is to improve the packet classification technology from the data level.Therefore,a Hardware Packet Classifier Coprocessor that can assist network processors and other devices in packet classification is proposed to further reduce the impact of range expansion.This paper uses verilog HDL to design the Hardware Packet Classifier Coprocessor,including Context Buffer,Key Process Unit,Database Array,User Data Array and Result Buffer.Context Buffer are used to load and store primary lookup key from the main processor,ASIC or FPGA.Four parallel Key Process Unit are used for encoding,copying and reorganizing the search key to adapt the format of classification rules stored in the Database Array.Database Array mainly realizes the matching process between search key and classification rules,changes the search unit inside TCAM,and adds a secondary search module for secondary C-TCAM storage structure.User Data Array is used to read the corresponding execution actions of matching classification rules.Result Buffer is used to store the execution action information read from User Data Array.In addition,the controller of the Hardware Packet Classifier Coprocessor is designed to control the functions of the coprocessor.Then this paper builds a verification platform for the Hardware Packet Classifier Coprocessor,and verifies the functions of each module and the master controller of the coprocessor.The results show that the functions of each module and master controller of the coprocessor can be realized correctly.Finally,the controller of Hardware Packet Classifier Coprocessor is synthesized logically and physically by using JAZZ 0.18?m technology.After synthesis,the working speed of the controller can reach 97MHz,the total area of the circuit is 565 9805.05?m~2,the leakage power consumption is 208.1742?W,and the dynamic power consumption is225.4812mW.The layout area is 1800?m x 1800?m.