Research Of Critical Techniques For FPGA Hardware Trojan Detection

Security concerns of field programmable gate arrays(FPGA)have been raised,with its wide applications in various critical fields.Attention has been drawn and researches have been conducted in the past few years regarding safety issues of FPGAs.Cyber security nowadays is no longer limited to software security alone,the hardware devices themselves are exposed to more and more possible threats.Hardware Trojan attacks,as one of the most effective way to attack a hardware device,have received massive attention from researchers in related fields.This thesis focuses on FPGA hardware Trojans,studied the side-channel based and the ring oscillator network(RON)based hardware Trojan detection technique,respectively.Main contents of this thesis are stated as follows:(1)Concepts and detection techniques of FPGA hardware Trojans are introduced.Structures and categories,principles and characteristics of FPGA hardware Trojans are analyzed.Existing detection techniques of FPGA hardware Trojans are summarized,and the advantages and disadvantages of existing techniques are illustrated.(2)An electromagnetic side-channel based Trojan detection technique concerning FPGA clock tree is proposed.For FPGA hardware Trojan detection,a side-channel based detection method is proposed in this thesis.First of all,the impacts of hardware Trojan insertion on the FPGA clock tree are specifically analyzed.Then,an experimental framework is proposed to acquire the electromagnetic side-channels of the FPGA clock tree.Last,two-dimensional principal component analysis(2DPCA)and back propagation neural network algorithm are introduced respectively to extract features from the electromagnetic side-channels and examine the presence of hardware Trojans in the FPGA under authentication.The experimental results show that the detection rate for always-on Trojans under tests are 100%,and up to 92% for triggered Trojan.In addition,the influence of five important experimental parameters,such as probe step and scanning area,on the detection results is discussed in detail.(3)An optimization method for RON based Trojan detection technique is established.For the on-chip RON Trojan detection technique,a framework to optimize the number of ROs is proposed.First,the principle of hardware Trojan detection using RON is introduced.Then,the perceivable range of a RO to Trojans of a specific size is studied.Based on this range,a RO placement scheme is proposed according to hexagonal lattice.And the placement of ROs at the boundaries of a circuit is discussed.The number of ROs to be used in a RON can be optimized with this placement scheme.Experimental results show that the proposed framework has advantages over existing placement reported in other researches on either RO number or Trojan detection accuracy.Furthermore,experiments on FPGAs of varying processes showed that the proposed method is general applicable.