Hardware Implementation Of Precise Synchronization And Multipath Resolution In Wireless Communication Systems

The problem of resolution and estimation of multipath signals has attracted widespread attention in the last century.Thus many related algorithms are put forward.To meet more strict requirements,the improvement of multipath resolution is critical in practice.Hence high multipath resolution algorithms become an important research area.In order to solve the time delay estimation of multipath signals,this thesis presents some traditional multipath resolution algorithms.Then,the hardware implementation of Taylor series expansion-based multipath resolution algorithm is presented.Furthermore,the corresponding hardware codes are optimized and tested.The main work of this thesis is as follows:Firstly,the research background and signal models are introduced.Then,the basic structures and development procedures of FPGA are presented.Moreover,some theoretical analysis and algorithms of multipath time-delay estimation are studied.Secondly,several high-precision multipath time-delay estimation algorithms are studied,including EM algorithm,WRELAX algorithm and multipath signal resolution algorithm based on Taylor series expansion.The improvement of Taylor series expansion based signal resolution algorithm is carried out especially for spread spectrum sequence signals.More than that,an adaptive threshold detection algorithm and fixed-point simulations are developed.Thirdly,the overall structure of the hardware implementation of Taylor series expansion based signal resolution algorithm is designed,and the hardware implementation of each submodule is implemented.These submodules include adaptive threshold part,parameter estimation part,signal recovery and temporary RAM update part,state machine part,capture module,correlation module and ram design.The Modelsim hardware simulation results of each module are consistent with the fixed-point simulation results of Matlab.Finally,static timing analysis is performed on the design,and the logic is optimized according to the analysis result,ie,multiplier optimization,reset signal design optimization,and system clock design optimization.Then the DDR2 interface design and implementation to improve the system hardware testing flexibility are studied.At last,the thesis uses Chipscope to carry out the actual measurement on each hardware module.The test results show that the submodules of the hardware design work normally and the indicators meet the design requirements.