Design And Simulation Of High-speed Physical Random Number Generator Chip

With the development of information technology,people are increasingly worried about information security.As an important part of the information transmission process,random number generator has attracted more and more attention.The unpredictable and non-reproducible random number sequence generated by it plays a vital role in information encryption.Based on Shannon's information theory,in order to ensure the absolute security of communication,high-speed,unpredictable and good randomness random number generator has great research value.Generally,random number generation methods can be divided into two categories: pseudo-random number generator and physical random number generator.The design of pseudo-random number generator is mainly composed of initial seed and deterministic algorithm.The more complex the deterministic algorithm is,the better the quality of the generated pseudo-random number sequence is.However,due to the determinacy of its nature and the fixed periodicity of its generating sequence,its application in the field of secure communication is limited.Physical Random Number Generator uses natural noise,such as thermal noise and jitter noise,to eliminate the periodicity problemof Pseudo Random Number Generator completely,which is of great significance to the application with specific requirements for the quality of random number.Because of the inherent unpredictability of physical noise sources,their development prospects are extremely broad.The common design schemes of physical random number generator include noise amplification,oscillation sampling,metastable and chaotic circuits,each of which has its own advantages and disadvantages.The scheme of generating random number by noise amplification method is simple and easy to implement,but because of its need to amplify weak noise and large power amplifier,the power consumption in integration is higher.In the practical design of oscillation sampling method,the timing jitter of actual oscillator is often insufficient.It is difficult to obtain a random number sequence with good distribution performance only by sampling the entropy source,and additional measures are often needed.Increase the timing jitter of the oscillator or take post-processing measures to improve its distribution characteristics.In metastable design scheme,power noise,temperature drift and process deviation have great influence on metastable circuit.Complex feedback regulation circuit is usually needed to correct the circuit of random number generator,which will introduce more complex influence.In this paper,a high performance random number generator is designed based on Boolean chaotic sampling method of logic gates.Using the non-ideal characteristics of real logic devices,the Boolean chaos with a bandwidth of about 800 MHz is generated.The schematic diagram and chiplayout are designed by Cadence software,and the simulation and random number quality test are carried out.The results show that the design can generate random number with good random performance.Number of machines.This paper focuses on the research and design of Boolean Chaotic Random Number Generator chip.1.A Boolean chaotic circuit is constructed by using simple logic gate circuit as a node.Its circuit characteristics are tested in the FPGA,and the dynamic characteristics of its entropy source and the quality of its random number are theoretically analyzed.2.Choose the circuit scheme of generating random number with good quality,complete the circuit diagram and layout design in Cadence,and carry out simulation analysis,collect the generated random number and test the quality of random number.