Design Of Image Acquisition And Preprocessing System Based On FPGA

Digital image processing is widely used and has important research value.With the increasing demand for the speed of digital image processing,the traditional image processing system has been difficult to meet the requirements.FPGAs have parallel features,and are especially suitable for algorithms that deal with the underlying parallelism of images,which can significantly increase the speed of the system.Therefore,image processing system based on FPGA has attracted more and more researchers' attention.This thesis designs an image acquisition and preprocessing system based on FPGA.The system mainly includes an image acquisition module,an image processing module,an image buffer module and a VGA display module.Firstly,this thesis introduces the principle and design method of FPGA,then studies the low-power finite state machine in digital integrated circuits,gives a method of describing finite state machine based on graph theory,and establishes a mathematical model of low-power finite state machine coding.Then this thesis designs the circuit of the image acquisition module,the image buffer module and the VGA display module by hardware description language.The image acquisition module includes the configuration of the camera register and the acquisition of video data.In order to coordinate the various modules of the system,this thesis uses asynchronous FIFO and SDRAM as image caching modules.In this thesis,a general asynchronous FIFO is designed and a design method of asynchronous FIFO with arbitrary even depth is proposed based on the mirror symmetry of Gray code.This method can improve the utilization of asynchronous FIFO and reduce the consumption of hardware resources.The processed image data is cached into SDRAM by SDRAM controller,and then is output to external display according to the timing requirements of VGA interface.Image filtering and edge detection are the most basic parts of image processing.The image processing module in this thesis mainly focuses on image filtering and edge detection.This thesis focuses on the design and implementation of an improved Sobel edge detection system based on FPGA.By means of selective median filtering,the system can remove noise and better protect edge information.Aiming at the fixed threshold selection of traditional Sobel edge detection operator,this thesis proposes a threshold adaptive Sobel edge detection method.The method adaptively generates the threshold by the average value of the brightness of the image region,which improves the accuracy of the edge detection to some extent.This thesis uses Matlab software to simulate the algorithm,and realizes the image processing algorithm module by using the parallelism and pipeline operation of FPGA.The simulation results on Modelsim software show that each module circuit meets the design requirements.In this paper,the designed circuit is compiled and synthesized on Quartus software,and then is downloaded to the FPGA chip.Finally,an image processing system with a speed of 30 FPS and a resolution of 640*480 is realized,and the system has a better detection effect than the traditional Sobel edge detection algorithm.