Design Of LiDAR Image Chip Based On Time Of Flight Principle

Firstly,the basic principle and module of Time of Flight LiDAR(Light Detection and Ranging)imaging chip are introduced in this paper.It illuminates the target object by transmitting laser pulse and receives the reflected laser pulse signal by receiver chip of LiDAR.The flight time of the optical signal is obtained by received time of the laser echo signal to measure the distance of the target object.Comparing the difference of the return time of laser pulse received by different pixel units to form the digital 3D expression of the target,and finally to form the 3D image through data processing.In receiver chip of LiDAR,the optical pulse is absorbed by the photodiode and converted into the photocurrent pulse signal.Then,the photocurrent is converted into the voltage pulse by Trans-Impedance Amplifier.The pulse voltage signal output by TIA is processed by Constant Fraction Discriminator module for the input of comparator,the comparator is triggered by pulse signal to output square wave pulse signal;the square wave pulse is time standard of Time-to-Amplitude Converter,and time information is converted to analog voltage.Finally,Analog-to-Digital Converter converts the analog voltage to digital signal.Among them,CFD and TAC modules play a decisive role in quantifying the flight time of laser pulse signal,and their timing accuracy and timeamplitude conversion accuracy determine the measurement accuracy of the whole LiDAR receiver chip.Therefore,based on the basic principle of CFD,this paper designs several timing circuit structures for LiDAR receiver chip,and tests the pixel TAC chips.After briefly introducing the principle of ToF LiDAR chip,this paper analyzes the basic principle of CFD module in detail.Besides,based on the shortcomings of traditional circuit structure,a new narrow pulse delay circuit is proposed in this paper,and improves the attenuation circuit of traditional resistive voltage divider structure.A high timing accuracy CFD circuit is realized with the new narrow pulse delay circuit.Among them,the narrow pulse delay circuit proposed in this paper solves the problem of pulse waveform distortion caused by the traditional RC delay structure,and effectively reduces the timing error caused by the nonlinearity of waveform distortion.Besides,based on the traditional CFD circuit structure,two new pulse timing methods are proposed.Based on the 0.18?m CMOS process,the three timing schemes are simulated by Cadence IC616.In the basic principle analysis of the timing scheme,the simulation verification is carried out in this paper.The time walk reduced by three pulse timing schemes proposed in this paper.The time discrimination achieves a minimum time walk of only 73.6 ps.The traditional CFD timing scheme with the smallest timing error is used to design the layout.The final module chip area is 122?m×74?m,and the overall chip area is 290?m×186?m.The overall chip area includes not only the TAC module,but also the pre-stage TIA module and the pseudo-TIA module that provides the bias,as well as a reference module that provides a stable bias for the entire chip and a buffer that stabilizes the bias voltage.