The Design And Implementation Of A Error-checking-and-correction Algorithm Based On BCH Architecture

As technology advances,a variety of intelligent electronic devices have emerged one after another,and portable storage has gradually become indispensable.Usually,the information state of the internal storage medium of portable storage is easily affected by the external environment,and the correctness of information access is precisely a prerequisite for the normal operation of portable storage.Therefore,manufacturers of portable storage products often insert ECC algorithm modules into their products to improve the accuracy of product information access.And BCH is just such an ECC algorithm which is widely used in the field of portable storage and has a high cost performance.In order to realize a BCH algorithm module with strong error-correcting ability,small area and zero delay,this paper designs a BCH test chip with SilTerra CMOS 180 nm Logic technology process,and finally realizes a BCH test chip which supports maximum 1K Bytes data encoding and maximum 72 bits error-correcting.This paper focuses on the research and analysis of the basic concepts,working principles,algorithm architecture and physical implementation of BCH algorithm,and puts forward the specific ideas of BCH algorithm implementation,and finally completes the code design,back-end design,GDS tape out and product testing of BCH algorithm module.The main contents are as follows:Firstly,the basic concepts and algorithm principles of BCH are studied carefully.According to the algorithm architecture,the model is built by Matlab.The feasibility and performance of the BCH algorithm are verified,and the parameters of the algorithm are optimized.Secondly,the algorithm validated by Matlab is decomposed into two modules: encoding module and decoding module.Among them,the encoding module is relatively simple,while the decoding module is more complex.According to different functions,the decoding module is divided into three parts: adjoint computing,BM iteration and chien search.Next,according to the requirement of product,the architecture of encoding module and BM iteration module is optimized,which further reduces the difficulty of physical implementation and improves the efficiency of the system.Among them,it is particularly important to adopt the irreversible BM iteration algorithm,which eliminates the division operation which is difficult to implement in the original BM algorithm architecture,and makes the physical implementation of BCH algorithm simpler and easier.Finally,the code design and simulation verification of BCH algorithm are carried out by using Verilog,the corresponding back-end design is completed,and the verification is carried out on the SilTerra 180 nm process.After the production of the chip is completed,the error-correcting ability of the test chip embedded in the BCH algorithm is tested in all directions.Finally,all the test results have passed the system examination.The results show that the goal of realizing the BCH algorithm module is successfully completed.