High Performance Improvement Of Named Data Network Routers

Internet users are interested in the content of the data and don't care where it is located.However,TCP/IP networks still need to establish end-to-end connections for communication.Because routing nodes do not have the ability of data caching,duplicate data in the network can not be reused.Connections need to be re-established after the location of both sides connection changes,so the mobility support is not friendly.Communication data is not secure without application layer encryption.There are many problems in TCP/IP,which need a new network mode to solve.Named Data Network(NDN)can satisfy the new content-based network mode demand.Using the advantages of name routing,data cache and packet encryption,the defects in current TCP/IP network design are solved.However,most of the research on NDN focuses on the protocol improvment.But this new network is facing great challenges in the transition and deployment phase.It needs high-performance software routing to work on the existing universal servers to avoid the huge cost of large-scale hardware upgrade.And this thesis designs and implements a high-performance software architecture for named data network routers,and achieves the performance goal of high packet forwarding rate through various optimization techniques.This thesis analyses the performance bottlenecks of software routers with high packet forwarding rate on current hardware platforms,and then designs a name prefix lookup algorithm and implementation strategy to eliminate these bottlenecks.The analysis reveals that memory access latency is one of bottlenecks for high speed forwarding engines,So this thesis proposes a novel data structure of second-phase Bloom filter to reduce the number of memory accesses,the name search can be completed on CPU cache without memory accesses.Using the technology of network data packet processing based on user space,the frequent I/O interruption of the operating system kernel protocol stack is avoided.At the same time,the performance bottlenecks in the network packet forwarding process are analyzed from the micro-architecture.Then two prefetch-friendly packet prefetching technologies are designed to hide the DRAM access delay and reduce the CPU flow pause.Network packet processing is fixed on a specific logic processor to avoid cache loss.question with multi-core programming and network card multi-queue design.In this thesis,we deploy this implementation on the general hardware server,and analyze the impact of different prefetching strategies,the number of threads and the size of forwarding routing table on packet forwarding rate.The analysis of data results shows that the implementation can achieve 10 Mpps packet forwarding rate and10Gbit/s line speed throughput when the size of the packet is 100 bytes,which achieves the design goal of this thesis.