Research And Design Of High-order Cascade N-Path Filter Based On Adjoint Network

In recent years,N-path filters have been widely used in various fields such as communication and radio.With the advancement of analog integration processes and the development of communication systems,N-path filters have received widespread attention,with center frequencies controlled by external clocks and dynamically adjustable ranges.Theoretically,the tuning frequency of the N-path filter is independent of the circuit components and dimensions,and is only related to the frequency of the switch,so it has a very wide tuning range.This advantage makes the N-path filter a new idea in the design of the RF receiver front-end architecture.This paper aims to study the design of high-order cascade N-path filters and the analysis methods based on adjoint networks.First,the basic theory of N-path filtering technology and adjoint networks is analyzed in detail.Second,the main performance indexes and requirements of the N-path filter are introduced in detail.According to the current N-path filter,there are problems such as large loss,low suppression,high noise and narrow tuning range.The study designed the following three high-order cascade N-path filters.Finally,The N-path filters studied and designed were simulated and verified by Matlab and Cadence software.The main work and innovation of the thesis are as follows:(1)Research and design a CMOS wideband distributed adjustable N-path filter.The MOS switch in the circuit is controlled by an external differential clock,which can eliminate the interference of even harmonics in the filtering process.The designed circuit is simple in structure and easy to set up.The transfer function of the N-path filter is derived by using an analysis method based on the adjoint network.The result of using the Matlab simulation transfer function is compared with the result of the Cadence simulation circuit design.It shows that the theoretical analysis is in good agreement with the simulation design results.In the TSMC 0.18 um CMOS process,when the power supply voltage is 1.2V,the center frequency of the circuit can be adjusted from 0.4 to 1.6 GHz,the in-band loss is about 34 dB,and the out-of-band rejection is as high as 72 dB.(2)Research and design a high-order N-path filter with low loss,low noise and wide tuning.By introducing a series inductor in a conventional first-order N-channel filter and cascading it,a high-order cascade N-path filter is obtained.The introduced series inductor resonates with the capacitor,reducing the loss and noise of the filter and extending the tunable range of the center frequency.The transfer function of the high-order N-path filter is derived based on the adjoint network method.The use of the adjoint network method greatly simplifies the mathematical derivation of the transfer function.The Cadence simulation results in the TSMC 0.18 um CMOS process show the correctness of the transfer function.The Cadence simulation results also show that when the power supply voltage is 1.2V,the center frequency of the high-order N-path filter can be adjusted from 0.4-3.0GHz,the in-band loss is 11.6dB,and the noise figure is 0.2-0.8dB.(3)Research and design an improved high-order differential N-path filter.The MOS switch in the circuit is controlled by an external differential clock,which can eliminate the interference of even harmonics in the filtering process.At the same time,the input transformer is connected to the input and output ports to ensure the impedance matching of the input and output signals.The transfer function of the high-order differential N-path filter is derived by using a method based on the adjoint network.In the TSMC 0.18 um CMOS process,when the power supply voltage is 1.2V,it has a center frequency adjustable range of 0.2-3.0GHz,an out-of-band rejection is higher than 58 dB,and a noise figure of 4.6dB.These three high-order N-path filters achieve low loss,low noise,high rejection,and wide tuning.The second filter is a simplified design of the first filter,and the third filter is an improvement of the first two filters.These three high-order N-path filters are based on the theoretical research of the adjoint network analysis method,and the simulation results of the theoretical analysis results are verified by Matlab simulation software.In the TSMC 0.18 um CMOS process,The design and pre-simulation and post-simulation verification of its circuit structure were carried out by Cadence simulation design software.The research results show that the theory and design of the three high-order N-path filters are in good agreement,the front-end simulation is well matched,and the circuit structure is simple and easy to set up,which is suitable for high-performance receivers.