Implementation And Testing Of IEEE 802.1AS Protocol

In recent years,the Internet is gradually expanding into the manufacturing sector.The combination of the Internet and traditional industries in various countries has promoted the birth of the Industrial Internet.The Industrial Internet is a global network that connects upper-level information technology with lower-level operational technologies and uses big data for analysis to provide a smarter production environment and higher productivity for the current industry.In order to adapt to both traditional industrial control and emerging artificial intelligence,the industrial Internet needs to improve the traditional network system to meet the requirements of large bandwidth,good synchronization,strong stability,good interoperability,small delay and less packet loss.Time-Sensitive Networking(TSN)is such an Ethernet extension standard cluster that satisfies the diversity and differentiation needs of various fields and applications.It is considered to be the development direction of the future industrial Internet.As the basis of the TSN standard cluster,the IEEE 802.1AS protocol provides the most basic time synchronization function for other standards in the TSN.Implementing and testing the IEEE 802.1AS protocol is of great significance for understanding TSN.Based on the analysis of the functional division of IEEE 802.1AS protocol,this paper proposes three implementable design schemes based on the specific Zedboard hardware environment.The advantages and disadvantages of each scheme are analyzed,and the time synchronization performance,ease of implementation,maintenance and scalability are considered.Finally,an IEEE 802.1AS protocol implementation scheme based on hardware IP core is selected.In order to realize this solution,this topic first configures the Zedboard development board at the hardware level,connects the MAC controller with the physical layer chip of the PL end to ensure the formation of hardware paths,and then designs the tunable real-time clock and automatic in the hardware IP core respectively.The hardware timestamp of the time of the entry and exit of the packet is recorded and encapsulated by the register module for the processor to read and write.On top of the hardware,this topic develops a driver for the hardware IP core based on the Platform bus mechanism in Linux,and provides operations such as clock reading,frequency modulation phase modulation,and time stamp acquisition for the application layer software.At the software level,based on the development of gptp by Avnu Alliance,the cutting and porting in the embedded environment is carried out on it,the driver of the hardware IP core is added to interact with it,and the software is optimized to improve the synchronization precision.Finally,the synchronous performance test of the whole implementation scheme is carried out.The distance between the main clock and the rising edge of the slave clock pulse output is observed using an oscilloscope,and the synchronization precision of the two nodes is estimated.In addition,the optimization algorithm of the software layer is verified,and the correctness of the algorithm is proved according to the comparison of the test results.Through experimental tests,the implementation of this project enables two nodes in the clock domain to achieve sub-microsecond synchronization.