Research And Implementation Of Polar Decoding Algorithm For 5G System

Polar codes,proposed by professor Arikan,have been proven mathematically that the shannon limit is achievable when the code length tends to infinity.Compared with the traditional channel codes,polar codes can adapt to the rate matching requirements in various scenarios.Polar codes also have clear construction method and with no error floor,making polar code catched up and became the channel coding scheme of the control channel in the 5th Generation of Mobile Communication System（5G）of enhanced Mobile Broadband（eMBB）scenario.The decoding performance is not ideal due to the characteristics of the serial processing of the successive cancellation（SC）decoding scheme.The successive cancellation list（SCL）decoding scheme can solve this problem effectively and with large performance gain,but the complexity is high.Therefore,it is significant for the implementation of polar decoder to reduce the complexity under the premise of maintaining excellent error correction performance.With the support of the“Enhanced Mobile Broadband 5G Terminal Simulator R&D”project,the decoding algorithms of 5G New Radio（NR）of polar codes are studied deeply.The research work and innovations are as follows:1.For the problem of high complexity of SC decoding algorithm and poor performance of min-sum decoding algorithm,a quantized sum product（QSP）algorithm is proposed.The QSP function is used to replace the hyperbolic function operation in the SC decoding algorithm,that is,only multiplication and addition operations are needed,which reduces the computational complexity and is easy to implement in hardware.Simulation results show that the performance loss of the proposed quantized sum product algorithm is less than 0.1dB compared with the SC decoding algorithm.A performance gain of about 0.4dB can be achieved in comparison with previous piece-wise linear approximation algorithm when the bit error rate is 10^-4.Compared with SC decoding algorithm and min-sum decoding algorithm,the proposed algorithm tradeoff between the high computational complexity of SC decoding algorithm and the low performance of min-sum algorithm.The proposed algorithm is transplanted into the SCL algorithm,and has the similar performance.2.The design and implementation of the transmitter and receiver of the physical downlink control channel transmitter and receiver is completed on the digital signal processor（DSP）,and the design is verified to be consistent with the technical specification of 5G NR in signal&spectrum analyzer ROHDE&SCHWARZ FSW200.Since the existing DSP chip does not have an associated Polar decoder coprocessor,for the issue of the DSP implementation of polar code,a cyclic redundancy check（CRC）assisted SCL decoding architecture based on TMS320C6678multi-core digital signal processor is proposed.Each module of the architecture is implemented with C language,and the processing element（PE）architecture is designed in detail.Compared to the SCL scheme,the proposed quantized sum product scheme reduced the processing time of the PE by a factor of 17 times,making a reasonable use of limited hardware resources and increased hardware processing fficiency.