The Research And Validation Of Accelerated Compression Coding In Parallel Based On Hardware Platform

With the development of Internet and artificial intelligence,a large amount of data is produced all the time.So,storage and transmission of data is very important.Appropriate data-compressing-algorithm can help reduce transmission bandwidth and save storage space.Meanwhile,the speed of data compressing and decompressing can directly influence the throughput of data processing system and network system.On the other hand,compared with CPU,FPGA and GPU have an advantage of dealing with massive data in a parallel way.Therefore,this paper do a research of data compressing and decompressing in a parallel way based on hardware platform.Firstly,this paper proposed a parallel structure for FAST protocol decoding adapting to 10 Gbps bandwidth based on hardware platform.The structure is composed of field dividing module,field matching module and parallel decoding units.Modeling and simulating the structure are done with SystemC platform,and the result shows that it takes about 435 ns to decode a FAST message including 64 fields.The performance is better than previous researches.Then,this paper efficiently realizes the deflate algorithm on xilinx:ad m-pcie-7v3 development board based on OpenCL language.Test results show that the maximum speed of compression is 3019MB/s,and the compression ratio is about 2.48 based on Calgary test sets.Compared with software solution,this solution could keep the compression ratio on the whole and the compression speed is 6.2 times as fast as the software solution.At last,compared with traditional development pattern with Verilog,developing FPGA with OpenCL in this paper could promote the efficiency obviously which has big practical application value.