Research And Design Of 45nm CMOS Based Analog Beamforming Receiver Front-end Chip

This thesis designs an analog beamforming receiver front-end chip with four channels.Each channel consists of a low noise amplifier,a mixer,and a phase shifter.The clock generator generates four 25%duty cycle square wave signals that do not overlap,to drive the four channel mixers.Under the premise of clarifying the design parameters of each module and the whole,the whole circuit design and the test of the four-channel analog beamforming receiver front-end are completed,and the characteristics of beamforming and interference cancellation are studied.Excellent communication quality requires low noise figure and high linearity at the receiving front end;good beamforming effect requires high accuracy of the phase shifter;long standby time requires low power consumption of the circuit.In order to meet the above requirements of wireless mobile communication systems,a novel analog beamforming receiver front-end structure is proposed.In the proposed receiver front end,the low noise amplifier,the active mixer,and the reconfigurable switch are stacked,the signal received by the antenna is amplified and downconverted to the intermediate frequency,and the current is reused from the radio frequency to the baseband,reducing the power consumption of the receiver front-end circuit;a set of parallel passive mixers translates the impedance of the baseband to the radio frequency end to achieve input impedance matching,which is defined by the local oscillator signal;the phase shifting function consists of the orthogonal active mixer and reconfigurable switch,using constant transconductance vector modulation technology.The orthogonal intermediate frequency current signal output by the active mixer is weighted and commutated by the reconfigurable switch,and finally converted by the load into the phase-shifted intermediate frequency voltage signal.The clock generator adopts a divider-by-2 and an AND gate structure.The divider-by-2 first generates orthogonal square wave signals with a 50% duty cycle and then performs an AND operation through the AND gate to obtain a square wave of 25% duty cycle.The intermediate frequency signals of the four receiving channels are directly combined in the current domain and converted to the intermediate frequency voltage signal at the load.The four 25% duty cycle square wave signals output by the clock generator provide drive signals with good amplitude and phase consistency for the mixers of each channel through the H-type clock drive network.The phase shifters of each receiving channel are individually controlled through the serial peripheral interface to implement beamforming and interference cancellation.This thesis focuses on the important issues in the design of analog beamforming receiver front-end chip layout,gives the layout process and basic principles,and completes the design of the analog beamforming receiver front-end layout according to the above procedures and principles.The four-channel receiver frontend is implemented in a 40 nm CMOS process and is verified and tested.According to the test results,S11 is less than-10 dB,the noise figure is 5.0 dB,the receiver front-end conversion gain is 21.1 dB,the intermediate frequency bandwidth is greater than 100 MHz,and the input reference P1 dB is-15.49 dBm,input reference IP3is-4.77 dBm,single channel power consumption is 3.81 mW,root-mean-square phase error is 1.59 degrees,and root-mean-square gain error is 0.27 dB.