Study On Reconfigurable Multi-mode Hardware Processing Structure Convolutional Neural Networks

Artificial intelligence technology is increasingly being used in people's living production.A large number of artificial intelligence products have been introduced in domestic and foreign enterprises.Major universities and research institutions also have a large number of technical achievements.The academic research on artificial intelligence technology is still rising.Artificial intelligence has become one of the most influential technologies of the modern era.Convolutional neural networks have an important position in the development of artificial intelligence.It has achieved outstanding results in the fields of image processing,target recogniti on,voice processing,and automatic driving.The structure of a convolutional neural network requires a large amount of computing resources and computation time,and the convolutional layer is the most computationally intensive part of the network.Earlier people used CPU to perform calculations,which was not efficient.Later,research results on the acceleration of convolutional neural networks using GPU,FPGA,and ASIC technology emerged.Among them,ASIC has certain advantages in terms of performance,area and power consumption relative to GPU and FPGA.To improve the computational capabilities and reduce the power consumption of the structure.The design analyzes the structural characteristics of the convolutional neural network.In this paper,the hardware operation processing structure of convolutional neural network is studied and designed.It is a reconfigurable and multi-mode structure.By combining some features of classic convolutional neural network model such as AlexNet,GoogleNet,ResNet,etc.The design uses a reconfigurable convolution unit.The convolution operation unit is then structurally partitioned and optimized.The design builds a reconfigurable array structure that supports multiple data patterns.The structure contains 24 basic unit s(PEs)capable of supporting 8-bit fixed-point and 16-bit fixed-point convolution operations.By reasonably allocating data in different modes,the structure can support convolution operations of different sizes such as 1×1,3×3,5×5,and 7×7.A booth coding and tree multiplier structure is utilized inside the PE unit.The array has some improvements in terms of computational efficiency and power consumption.Combined with the storage structure,the acceleration performance has been improved.At 500 MHz and 1 V,this design has an increase of area consumption about 19% to 46% compared to a typical single-mode operation structure,but power consumption is reduced by approximately 52%.Combined with the memory structure,the multi-mode operation acceleration structure uses 640 MHz,1 V.In 16-bit fixed-point mode,the peak performance is 276.5 GOPS and the total power consumption is 599 mW.The analysis was performed on the AlexNet,GoogleNet,and ResNet-34 layer convolutional neural network structures,respectively.And the structures were able to achieve frame rates of 176.7 fps,75.4 fps,and 36.7 fps,respectively.In 8-bit fixed-point mode,the peak performance is 1105.9 GOPS,power consumption is 599 mW,frame rate is 737.2 fps on AlexNet,318.8 fps on GoogLeNet,and 135.6 fps on ResNet-34.Compared with similar literature,the calculation efficiency,energy efficiency and area efficiency have increased by 1.16 times,1.17 times and 2.4 times,respectively.The structure of this design has an important role and application prospect for the acceleration processing of convolutional neural networks.