Study On Encoding And Decoding Algorithms Of LDPC Codes Based On Multi-core Processor

As a class of great error correcting channel codes,Low-Density Parity-Check?LDPC?codes have gained widespread attention for more than 20 years.The low complexity encoding and decoding algorithms of LDPC codes promote their implementation in various communication systems.The improvement in performance of general purpose processor accelerates the Software-Defined-Radio?SDR?development.This thesis will focus on the study of encoding and decoding algorithms of LDPC codes and the software encoder and decoder design and implementation for LDPC codes based on Single Instruction Multiple Data?SIMD?instruction set and multi-core processor.In the first chapter,we introduce the background and research status of the subject.Firstly,we briefly introduce the basic knowledge and research status of the LDPC codes.Then,we describe the parallel pro-cessing techniques of processor and give the research status of the software decoders for LDPC codes based on programable devices.Finally,we explain the organizational structure of this paper.In the second chapter,the LDPC codes for 5G standard and the encoding and decoding algorithms of LDPC codes are introduced.Firstly,the encoding procedures for 5G enhanced-Mobile-Broadband?eMBB?data channel are introduced,including Cyclic Redundancy Check?CRC?calculation,code block segmentation and rate matching.Secondly,we give the encoding algorithm of Gaussian elimination and the block cumu-lative encoding algorithm for quasi-cyclic dual-diagonal structure LDPC codes separately.Finally,Belief-Propagation?BP?decoding algorithm in log-domain and its simplified algorithms are described in detail,and the horizontal layered decoding deployment is introduced.Combined with the 5G-LDPC codes,the Block-Error-Rate?BLER?of various decoding algorithms and the convergence speed between flooding decoding and layered decoding are given.In the third chapter,the designs of encoder and decoder for rate-compatible LDPC codes based on SIMD instruction set are given.Firstly,we briefly introduce the SIMD instruction set and the Cache techniques,and give a direction for software optimization.Then,we describe the encoder of Gaussian elimination and block cumulative in detail separately.The block cumulative encoder for 5G-LDPC code of information length K=8448 and code rate R=11/12 can achieve 2169Mbps information throughput in SSE mode on a single core.Finally,we propose a design for rate-compatible LDPC codes based on SIMD instruction set.Throughput up to 81Mbps is achieved on a single core in AVX configuration when executing 20 fixed decoding iterations for 5G-LDPC code of information length K=8448 and code rate R=11/12.Compared with the related works,the proposed decoder can reduce the implementation and storage complexity through online calculation and the pre-configured calculation units of check nodes.In addition,our decoder has no performance loss for regular row weight LDPC codes compared with the previous decoders.In the fourth chapter,we discuss the software LDPC encoder and decoder implementation for 5G large-scale distributed Multiple-Input Multiple-Output?MIMO?test system and the error-floor simulation platform design for LDPC codes based on multi-core processor.Firstly,we introduce the basic architecture of 5G test system and give the design of LDPC encoder and decoder for the system and corresponding software implementation.The software is tested with the system.The system achieves 10.185Gbps throughput with12 users under actual air-interface test.Finally,we study the design of LDPC codes error-floor simulation platform based on multi-core processor.The concurrent design and software optimization are elaborated and the calculation ability of the platform in different threads and SIMD configurations is analyzed combined with specific LDPC codes.In the fifth chapter,we study the decoding performance of alternate direction method of multiplier-s linear programming?ADMM-LP?decoding algorithm for 5G-LDPC codes and discuss the corresponding implementation based on SIMD instruction set and multi-core processor.Firstly,the thesis describes the ADMM-LP algorithm.Experimentation results show that the ADMM-LP decoder has lower error-floor com-pared with the BP decoder,but the BLER performance of ADMM-LP decoder is inferior to BP decoder at low signal to noise ratio?SNR?values.The ADMM-LP-l₂decoder with penalty term can improve the decoding performance at low SNR values but the penalty parameters are difficult to search.Finally,we discuss the software implementation of ADMM-LP decoding algorithm based on SIMD instruction set and multi-core processor.The throughputs of the decoder are analyzed combined with LDPC codes.